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To: Paul Engel who wrote (147957)	11/14/2001 12:37:46 AM
From: brushwud	Read Replies (1) \| Respond to of 186894

Intel is making progress on Ovonics Memory technology... If you're impressed with Jerry Sanders, you'll love Stanford Ovshinsky, proponent of "ovonics". He's been trying to find an application for amorphous semiconductors for most of our lifetimes. One time it was for batteries, then it was for memories. His company, Energy Conversion Devices, parallels most closely Newport Pharmaceuticals, which had some drug that at first was going to cure herpes, then it was going to cure AIDS. "We're so busy with our own designs that we decided not to make this an internal effort," said Stefan Lai, vice president of Intel's technology and manufacturing group. Yeah, strong vote of confidence in this key emerging technology.

To: Paul Engel who wrote (147957)	11/14/2001 8:07:52 PM
From: Robert Salasidis	Read Replies (2) \| Respond to of 186894

Is that 1012 writes or 10^12 writes?

To: Paul Engel who wrote (147957)	11/18/2001 8:51:34 PM
From: wily	Read Replies (1) \| Respond to of 186894

Paul, what do you think it means that Intel is farming out the design work for the 4Mb test chip? If OUM was really important to them wouldn't they be doing it in-house? OTOH, they are working with Azalea also on their 4-bit/cell Flash. siliconstrategies.com They were very positive on OUM in July in their next-gen memory press bonanza: Intel Slideshow: intel.com Stefan Lai video interview: news.cnet.com EE-Times coverage: eetimes.com zdnet coverage: zdnet.com Any comments? wily

To: Paul Engel who wrote (147957)	12/11/2001 10:14:08 PM
From: wily	Read Replies (2) \| Respond to of 186894

Paul, Intel and Ovonyx presented a paper on OUM at IEDM -- the presentation and paper are posted on the Intel website: intel.com intel.com It sounds like CMOS integration is not considered a problem. My guess is that the major hurdle is narrowing the contacts to dimensions far below the lithography minimum line width, i.e., their goal is 70nm. They say they need this width to get the desired 1mA write current, but I'm wondering if they could compromise for a wider contact and higher current and still have a very advantageous memory. Maybe there will be more details at ISSCC? I doubt it. wily