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To: Gopher Broke who wrote (64054)	11/19/2001 9:13:36 PM
From: combjelly	Read Replies (1) \| Respond to of 275872

"Am I right in thinking that this leakage is a result of contamination of the Si substrate?" Probably not. One likely source of the leakage is a by-product of the CMOS process. The 'C' in CMOS stands for complimentary, CMOS uses a transistor to pull the voltage up, and one to pull it to ground. To make a transition from high to low, the 'hi' transistor switches 'off', and the 'lo' transistor switches 'on'. This is why the traditional CMOS process drew so little power, only a little of the charge was wasted to change states, unlike PMOS or NMOS which had a resistor tied to the high or low rail for one of the states. Anyway, as speeds increased, this arrangement wound up drawing more and more power. For one, because the transistors cannot switch fast enough, there is a period of time where both transistors are 'on' at the same time, resulting a a direct short to ground. Another, and this is pertinent to this particular problem, to increase the switching speed the transistors don't switch 'off' all the way, i.e. they 'leak'. As geometries shrink, the resistance of the 'wires' increase, and so does the capacitance of the junctions. That results in slowing down the signal, so the transistors need to switch even faster. Using copper helps with the resistance problems, low-k dielectrics help with the capacitance problem. But at some point, you wind up burning a lot of power to increase the clock rate. It has been felt in the industry that 0.13 micron would be tricky because of these problems, Intel may have discovered that their process just isn't good enough at 0.13 micron. It very well may be that process tweaks will get them past this hump, but they may need to scrap their current process and develop another. Hence, no doubt, the race to 0.09 micron...