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To: combjelly who wrote (64136)	11/20/2001 5:11:32 PM
From: Bill Jackson	Respond to of 275872

combjelly, I had suspected that the close in cache needed to be the SRAM for the raw speed, as you confirmed. The L3 needs less speed, embedding it as DRAM and giving it some size would be doable at the smaller features sizes we are getting into these days on SOI with that floating capacitor. Might also take a far less frequent refresh pulse set since on SOI the leakage would be a lot less. I am not sure the refresh pulses are a large burden. It sems to me that they are a very low duty cyccle and consume only a fraction of a % of BW, not like the old days when you needed them as frequently as the clock/2 to keep the data alive. Bill Bill