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To: Ali Chen who wrote (64179)11/21/2001 1:19:23 AM
From: milo_moraiRead Replies (1) | Respond to of 275872
 
Ali, thank you for the links.. I always wish to read up more as well. I've not had to apply my Electronics background on a designing level for over a decade as my primary job is in Telecommunications and the focus is Optics and OC's, HSD networking, HFC plant, DS circuits, DCS and Circuit based switching which is slowing moving to Packet based switching.

But I still like these type of discussions as I enjoy learning and understanding the barriers that AMD and INTC face.

Milo



To: Ali Chen who wrote (64179)11/21/2001 1:32:42 AM
From: milo_moraiRespond to of 275872
 
<font color=blue>Where is TWY!. This URL is interesting. It talks about diamond

google.com

or the pdf version www-device.eecs.berkeley.edu

Figure 9: Diamond may allow for further
device scaling as it has a lower dielectric
constant than silicon.
Diamond material
parameters: k=5.7, Eg= 5.4eV, m*=0.2. All
devices have Tbody=5nm, Tox,eq=10Å, VDD=
1V, VT=0.4V.
Figure 7: Intrinsic gate delay (CV/Ion) vs. Ioff. Despite series
resistance introduced by the thin body and graded S/D doping
profiles, CV/Ion can still be scaled down. Tox,eq=10Å.
Figure 5: Ioff will increase as VT is
scaled down because the channel
potential barrier height is reduced.
VT is defined at Ids=50nA/mm.
N +Source
+Drain
T spacer
body
L gate
Gate
P
Figure 2: Off-state leak-
age is comprised of therm-T
ionic emission above and
quantum tunneling through
the channel potential
rier. Both are important in
the 10nm regime.
Figure 8: A semiconductor material with a lower k reduces DIBL and may allow for contin-
ued device scaling. Adjusting m* and Eg do not significantly affect Ioff. All devices have
Tbody=5nm, Tox,eq=10Å, VDD=1V, VT=0.4V.