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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (149117)	11/21/2001 11:54:28 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

McKinley Details from ISSCC 2002 Abstracts ! Looks like McKinley will be huge (465 sq. mm. - 220 Million Transistors !) - about the same size as Merced - but with HUGE caches - L1 (16 KB - Single Cycle Read Latency), L2 (256KB - 5-cycle Read latency) and L3 - 3 MegaBytes - 4 Cycle Read Latency). This is built on the "older" aluminum 0.18 micron process - and most speed estimates are for 1.0 to 1.2 GHz Operation. Interesting trade-offs on the various caches - Lower latency read accesses with lower bandwidth - and higher latencies with FASTER read access bandwidth. {===================================} 20.6 The Implementation of the Next-Generation 646 Itanium TM Microprocessor 11:15 AM S. D Naffziger 1 , G. Hammond 2 1 Hewlett Packard, Fort Collins, CO 2 Intel, Fort Collins, CO The processor incorporates over 220M transistors on a 465mm^2 die and operates at >1.2GHz with an 8-stage pipeline in a 0.18µm process. It has three levels of on-chip cache totaling over 3.3MB providing >32GB/s bandwidth at each level. {=================================} 6.6 The 16kB Single-Cycle-Read-Access Cache on a Next-Generation 64b Itanium Microprocessor 4:15 PM D. E Bradley 1 , P. Mahoney 2 , B. Stackhouse 1 1 Hewlett Packard, Fort Collins, CO 2 Intel Corp., Fort Collins, CO A 16kB four-ported physically addressed cache operates at 1.2GHz with 19.2GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2x1.8mm 2 in a 0.18µm process. 6.7 An On-Chip 3MB Subarray-Based 3 rd -Level Cache for a Next-Generation 64b Itanium Microprocessor 4:45 PM D. Weiss 1 , J. Wuu 1 , V. Chin 2 1 Hewlett-Packard, Fort Collins, CO 2 Intel Corp., Santa Clara, CA This 3MB on-chip level-three cache employs subarray design style, and achieves 85% array efficiency. Characterized to operate up to 1.2GHz, the cache allows a store and a load in every four core cycles, and provides a total bandwidth of 64GB/s at 1.0GHz. {===================================} 25.5 The High-Bandwidth 256kB 2nd-Level Cache on an Itanium Microprocessor 3:45 PM T. Grutkowski 1 , R. Riedlinger 2 1 Intel, Santa Clara, CA 2 Hewlett Packard, Fort Collins, CO A second-level 256kB unified cache is incorporated into a 1.2GHz next-generation Itanium Microprocessor. The datapath structures provide a non-blocking, out-of-order interface to the processor core achieving a minimum 5-cycle latency with a stand-alone bandwidth of 72GB/s.