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To: Paul Engel who wrote (149265)11/23/2001 11:45:20 PM
From: wanna_bmw  Read Replies (1) | Respond to of 186894
 
Paul, Re: "Intel has new process technologies in development that compete with SOI - but have no drawbacks with floating substrate issues !"

That should give the 'Droids something to think about. Now, if it can only be cheaper to manufacture than SOI, and offer higher yields, AMD would be in for a world of hurt. 50nm transistors will probably align with Intel's .09u technology node, which should make things very interesting, come 2003.

SOI certainly isn't looking so rosy anymore.

wbmw



To: Paul Engel who wrote (149265)11/24/2001 12:01:20 AM
From: Elmer  Read Replies (3) | Respond to of 186894
 
A 50nm Depleted-Substrate CMOS Transistor (DST)

While I'm not a process kind of guy I'm not ignorant either. This is great stuff!! Why is it that we never see AMD presenting "knock your socks off" presentations on process technology?

EP



To: Paul Engel who wrote (149265)11/24/2001 12:10:25 PM
From: Tony Viola  Read Replies (2) | Respond to of 186894
 
Paul, thanks for your three posts on Intel's breakthroughs in process technology that you dug out of the 2001 IEDM Technical Program papers.>

Intel has new process technologies in development that compete with SOI - but have no drawbacks with floating substrate issues !

Intel's 130nm logic technology has been ramped to high volume in multiple factores on on both 200mm and 300mm production lines.

An Enhanced 130nm Generation Logic Technology Featuring 60nm Transistors Optimized for High Performance and Low Power at 0.7 - 1.4V,

I wouldn't have found that 2001 IEDM Technical Program, much less read it or gotten the whole significance of the articles.

Thanks again,

Tony



To: Paul Engel who wrote (149265)11/24/2001 1:35:43 PM
From: kapkan4u  Read Replies (3) | Respond to of 186894
 
<Intel has new process technologies in development that compete with SOI - but have no drawbacks with floating substrate issues !>

Umm, cough, cough. Excuse me for doubting the great process expert, but this paper describes an SOI device:

"In this paper we show a 50nm depleted-substrate CMOS transistor (DST) technology fabricated on thin-silicon body"

What do you think the "thin-silicon body" means?


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