Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: wanna_bmw who wrote (149387)	11/25/2001 10:28:35 PM
From: Tony Viola	Respond to of 186894

Beamer, Maui, Maui, Re: "Does anyone know if 116mm squared includes the size of the cache ? If so, that would be a very impressive P4 shrink." >>This is probably without the cache. Why would it be quoted without the cache included (assume we mean L2 cache here)? It's on chip just as much as the CPU is. Tony

To: wanna_bmw who wrote (149387)	11/26/2001 9:06:10 PM
From: maui_dude	Read Replies (1) \| Respond to of 186894

Beamer, Re : "that Intel tends to have very high yields, overall (both line yields and die yields), so even if AMD has the advantage of smaller sizes, it doesn't do them very good if they are yielding low." I wish Intel is not thinking and planning based on AMDs lower yields. If they are not competitive based on cost, they better accelerate the hyperthreading roadmap or reduce the P4 die size (or accelerate 300 mm and .09). I agree with you, Intel is sitting quite pretty with desktops until Hammer comes out. They now have to find a way to not lose too much on the laptop segment until P4 .13 mobile is released. Maui.