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To: kinkblot who wrote (40)11/26/2001 5:05:26 PM
From: kinkblot  Read Replies (1) | Respond to of 83
 
EETimes: Intel does about-face on SOI

eetimes.com

Going to fully depleted SOI means wafers will have to be capped by layers of silicon as low as 30 nanometers thick, which is less than a third the thickness of partially depleted SOI. Wafer manufacturers' ability to control that ultra-thin layer is a "significant concern," Marcyk acknowledged.

According to André Auberton-Hervé, Soitec "just announced in July that we can get layers of silicon as thin as 30 nm." Here's a press release from July on their new thin-film UNIBOND wafers:

soitec.com

I read it twice and found only "as thin as 700 angstroms" and "below 1,000 angstroms," but perhaps he's referring to a different announcement. The product specs for Thin UNIBOND Wafers give the SOI layer thickness as 100 nm with a uniformity of 10 nm (max-min) for all three wafer diameters.

WT