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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: kapkan4u who wrote (149973)	11/28/2001 12:17:37 AM
From: milo_morai	Read Replies (1) \| Respond to of 186894

Well done Kap. Guess that ends the debate. IBM's been there and done that. M.

To: kapkan4u who wrote (149973)	11/28/2001 11:18:14 AM
From: fingolfen	Read Replies (1) \| Respond to of 186894

So your first argument that fully depleted SOI is something new is bogus. IBM, AMD and others have been looking at thin-film SOI for years. I apologize for not making my point more clear which has led to further confusion. I had read the article you mention, and was aware that others had worked on thin SOI. Albert and Co. seem fixated on the SOI portions of the transistor design presented by Intel, but ignore the raised S/D and high-k gate (the latter being a very significant inclusion). "Intel's decision to adopt high-k dielectric material for insertion beneath the transistor gate isn't surprising, since most IC manufacturers are moving in the same direction. High-k dielectric films promise to let chip makers grow a thicker insulation layer to reduce leakage while keeping capacitance constant." As a matter of fact, AMD has high-k SOI on their 90nm node roadmap. While IBM, AMD and other have been quietly researching these technologies for years, Intel woke up some day and pulled an overnighter wiz-bang slide picture show. Now I'm going to have to disagree with you there. Yes, Intel combined several features people have been working on for some time, but your accusation that they recently started this work is purely inflammatory. I did not in a previous message to Albert that taken one at a time, neither depleted SOI or high-k are new. I haven't seen anyone else combine them. What type of SOI is AMD looking at to combine with high-k? What film materials are they using? What deposition techniques? Looking at Intel's presentation (a previous poster listed the URL), it implies to me that they've been working on these for some time. "But IBM fellow Ghavam Shahidi said the history effect has been overblown. "The history effect is less [of an issue] for fully depleted SOI, but it is a very small effect to begin with, and it's hard to measure. I'm not sure why Intel is making it a big deal," he said. We have Intel fellows saying it's a big deal, and IBM fellows saying it isn't. Remember one thing: Intel has consistently demonstrated transistors smaller than ANYONE else in the industry. They started with the record setting 30nm transistor, and have followed that up with first a 20nm, and now apparently a 15nm. With all of their experience at small dimensions, perhaps Intel has discovered something that IBM doesn't know... In conclusion: Yes, IBM and others have worked on some of the building blocks of the transistor Intel presented. Intel, however, combined all of those blocks with transistor geometries no one else in the industry has reported as of yet. One would think rather than trying to spread FUD, the industry would want to know what Intel's really up to... Finally, even though the power point presentation tells a lot, and implies quite a bit of work, it's not going to tell anywhere near the whole story. This design (as well as several of the aspects in its fabrication) have most likely already been submitted to the U.S. Patent Office. Intel won't jeopardize patents in process by telling the whole story.