Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: milo_morai who wrote (150159)	11/28/2001 4:29:48 PM
From: Elmer	Read Replies (1) \| Respond to of 186894

I realize the competitive nature of the two companies, but INTC was denying SOI was necessary. Now it's Necessary. Milo you're trying to reinvent Intel's position. Intel has stated that SOI as implimented by IBM and AMD is not necessary. Their paper reinforces that. Their new process is not the same as IBM uses, it is more advanced and not necessary now. It will be necessary in 5 or so years. The fact that IBM couldn't get it to work hardly disproves Intel's ability. Try and be a little more accurate with your posts please. EP

To: milo_morai who wrote (150159)	11/28/2001 5:34:30 PM
From: fingolfen	Read Replies (2) \| Respond to of 186894

I realize the competitive nature of the two companies, but INTC was denying SOI was necessary. Now it's Necessary. Yes, but it's not SOI as it's being used now... Did you read IBM's SOI paper that Kap presented and how IBM had already looked at depleted SOI before. Looked at it... but did they combined depleted SOI with rased S/D regions? Did they further combine those two elements with a high-k gate? Technologies don't sit in a vacuum. Depleted SOI on it's own may not have been attractive to IBM (clearly wasn't). Conventional SOI doesn't sound like it was attractive to Intel. Depleted SOI + raised S/D + high-k does apparently hold some promise, however. Just because IBM looked at depleted SOI and rejected it doesn't mean that it won't work in conjunction with other process innovations. One of the most innovative portions of the new transistor presented by Intel was the raised S/D. Conventional CMOS transistors source, drain, well, and tip areas are flat. At least physically, the Intel transistor looks like it's halfway between a CMOS and a finfet. The functionality is more purely CMOS, but it's a very interesting approach to the problem. I have a copy of the presentation that Intel is presenting courtesy of whoever posted the link here on SI (Ten? semi? Elmer?), and it looks very promising. I'm really hoping for more information when Intel actually delivers the paper/presentation next week as there are some areas I'd like more information: Are they using conventional thin SOI wafers and then cutting a trench for the gate/spacer, or are they building up the S/D areas? Among others.