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To: Elmer who wrote (150182)11/28/2001 7:50:11 PM
From: milo_morai  Respond to of 186894
 
Thanx for looking up that Article Elmer

Mark T. Bohr, director of process architecture and integration at Intel Corp. and an Intel fellow, said Intel has concluded that any performance gains derived from SOI will diminish with every process generation, and that the downsides are too numerous.

In a slide presentation, Bohr showed figures indicating that extra performance derived from junction capacitance — the most compelling reason to choose SOI, he said — will start with a 13 percent improvement at 0.25 micron, fall to 10 percent at 0.18 micron and then to 8 percent at 0.13 micron. Other positive aspects were marginal and offset by negative factors, such as the floating-body effects caused by the transistor being isolated from the silicon.

He concluded by saying SOI provides less than a half-generation performance gain, has too many circuit-design uncertainties, adds another 10 percent to the process cost for an extra mask step, requires pricier wafers and may lead to yield loss.

Do you have more info on soft errors?

"It's still unproven for high-performance CPU applications," he said. "We see most of the SOI benefits holding constant, but the one key benefit is going to diminish."

He did agree, however, that SOI does have an advantage in preventing soft errors, an issue that has recently become a bigger concern for Intel as it scales its process technology below 0.25 micron. SOI is two to three times better than bulk silicon in preventing soft errors, which "may in the future be an argument for SOI," Bohr said.