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To: kapkan4u who wrote (150448)	11/29/2001 7:50:43 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Kap, Re: "I never claimed that this code is representative. The purpose of this code is to compare the performance of the PIII and P4 decoders to demonstrate that P4's decoder is running at half the clock. So If my thesis is correct a 1GHz PIII will beat 2.0GHz P4 because this code is forcing most work to be done in decoders." I don't believe this is a fair comparison. Of course if you force trace cache misses, you will see that one single decoder will not be able to perform as well as three separate decoders (as in the Pentium III). If you want to do this, you completely lose the concept behind the design. Even if Intel were to accommodate your application by adding several more decoders, that would be a lot of work, increasing die size, validation time, and design time, all for something that won't have much of a benefit in real world applications that don't miss the trace cache on every single load. You may be smart for an AMDroid, but you are still needing to pull your criticisms from overly obscure sources. Give it up - you're proving nothing. Re: "Yes this code is artificial, but no more so than the synthetic P4 memory bandwidth benchmarks that Intel proudly displays on every corner." I assume you are talking about the SiSoft Sandra memory bandwidth test. Maybe you can provide even a single link where Intel is displaying this? wbmw

To: kapkan4u who wrote (150448)	11/29/2001 8:25:36 PM
From: Road Walker	Respond to of 186894

kap, Are you still predicting that terrorists are going to put Anthrax into mall ventilation systems? How about the Japan like depression/recession (can't remember the exact details)? Or have you moved on to a new disaster? What's your paranoia du jour? John

To: kapkan4u who wrote (150448)	11/29/2001 9:12:14 PM
From: Timothy Liu	Read Replies (1) \| Respond to of 186894

Allow me to point out one thing. The program you present effectively is a test of processor stall. It penalize a more super pipelined processor like P4. This has nothing to do with the speed of the decoder. P4 has about 20 pipe line stages compare to PIII (10-15?). So it has to spend almost twice as much cycles to fill in the pipeline after a stall. The decoder frequency is irrelevant, even if the ID ran at 1/2 speed it must produce double output everytime otherwise it would not be a pipeline anymore. My 0.02. Tim