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To: wanna_bmw who wrote (150743)12/2/2001 8:07:41 PM
From: Dan3  Read Replies (1) | Respond to of 186894
 
Re: Intel has many fabs, but only a few of them are producing CPUs on the latest processes. Right now Intel has 1) Fab 20 in Oregon on .13u, 2) Fab D2 in California on .13u, 3) Fab 22 in Arizona on .13u, 4) Fab 14 in Ireland on .18u, 5) Fab 11 in New Mexico on .18u, 6) Fab 12 in Arizona on .18u, and 7) Fab 18 in Israel on .18u.

AMD is running one medium sized FAB, Austin, at (I would estimate) 3/4 capacity, and is ramping Dresden, which is at a little less than 3/4 capacity in terms of product shipped this quarter. Austin is 6K wspw and Dresden is supposed to be a 5K or 6K wspw (it seems to alternate each quarter). So, AMD is running .75 x 11 or 12K wspw. Several of Intel's CPU FABs run 10K wspw, several more are AMD sized, and several are in between. Given the money Intel has been spending, one would think those 7 FABs you listed are half fully ramped and perhaps half, half-ramped. But, most of the half ramped FABs are transitioning from .18 to .13, so they should already be producing more than 100% of their previous all .18 unit rate. The Intel CPU FABs probably average out to 6.5 to 8K wspw, so Intel is running something like 50K to 55K wspw to AMD's 12K wspw. While running 4.5 to 5 times as many wafers, they are producing 3 times as many good die - and, I'd guess we both think AMD is sitting on some excess capacity at the Austin "Duron" only FAB.

AMD's die are all 120mm2 to 130mm2. Intel is running about 1/2 217mm2 P4s, 1/6 .18 90mm2 PIII/Celeron, and 1/3 79mm2 Celeron and Mobile PIII/Celeron. So, Intel's average die size is about 150mm2, while AMD's average die size is about 125mm2.

Overall, I'd guess the two company's yields aren't terribly different - but that AMD's are noticeably better. Either that, or the rumor that SVG's delay of 193nm steppers has crippled Intel's .13 production is true.



To: wanna_bmw who wrote (150743)12/2/2001 8:24:27 PM
From: Dan3  Read Replies (1) | Respond to of 186894
 
Re: You seem to think that just because Intel is not using their version of SOI at the 130nm node, but they are using it at the 65nm node (and possibly the 90nm node), that they missed the boat, and now have to integrate it at a later time.

I think it is obvious that Intel got caught with its pants down.

Here's what Intel's director of process architecture and integration said last year at the same time AMD, IBM, Motorola, and the Taiwan foundries were already developing SOI processes. Following are additional comments from Intel senior engineer Kaizad Mistry on the results of Intel research into SOI processes and their conclusions:

"Good for them," said Mark Bohr, director of process architecture and integration at Intel's Hillsboro, Ore., facility, when presented with the growing list of companies adopting SOI for their high-end processors. "I don't want to change their minds," he said, adding that SOI may prove "very painful" for Intel's competitors....

Intel now acknowledges that at the 0.18-micron generation, SOI circuits run faster than bulk CMOS devices, largely because SOI effectively eliminates junction capacitance. However, as CMOS scales to 130 nm, 100 nm and beyond, SOI's performance edge will diminish, the company maintains, largely because junction capacitance will decline relative to total parasitic capacitance. Capacitance at the gate and in the interconnects will dominate at the 100-nm technology node and beyond, Intel holds....

Even as more companies gravitate toward SOI, others, including Intel, argue that simply scaling bulk CMOS brings an equal payback for the effort expended. And for high-volume, cost-sensitive products, the added wafer costs of SOI are significant, this camp holds....

Moreover, switching to SOI would require new EDA tooling, circuit models and training in "a tough design methodology," he said. Despite those difficulties, Intel would surely make the switch if convinced of the performance gains, said Intel senior engineer Kaizad Mistry. However, in what surely will be a much-debated paper, Mistry argued at the VLSI Technology Symposium that whatever speed advantages SOI technology may have at the 0.18-micron generation will diminish over time.

Intel created 0.18-micron SOI circuits, the "best reported to date" for 0.18-micron design rules, he said. Mistry's team in Portland, Ore., built test circuits using Intel's bulk 0.18-micron CMOS process and compared them to circuits adapted to SOI wafers. Mistry reported a 16 percent performance gain for SOI for an inverter with a fanout of 1, an 8 percent gain for an inverter with a more typical fanout of 4 and a 20 percent improvement for a three-input NAND.

That 15 percent gain was countered somewhat by the need to create a "guardband" for the so-called "history effect," reducing the net gain to only 10 percent, Mistry said. SOI transistors typically switch more slowly after an initial "on" state because the body is "floating" — that is, not connected to a grounded substrate. Since it is impossible to predict which transistors are suffering from the history effect, the circuit designer must create a guardband of 5 to 7 percent to ensure a predictable transistor performance on an MPU with millions of transistors, said Mistry.

The performance gain at 0.18-micron design rules might have tempted Intel, except that the wafer and design infrastructure was woefully lacking. The Intel team forecast that at the 0.13-micron generation, the performance gains stemming from the lack of junction capacitance in an SOI technology would diminish.

Intel believes that it is well ahead of other silicon vendors in terms of reducing junction capacitance in its bulk CMOS process. As scaling proceeds, and junction capacitance plays a smaller role vis-à-vis gate capacitance, the SOI advantage in terms of parasitics in the junction regions will fade to insignificance, the company contends.

Bottom line, by Mistry's accounting: By the 100-nm generation, SOI's advantage is only 3 percent. And that ignores the interconnect load, which erodes the SOI gain even further, Mistry said. For all of those reasons, SOI has no appeal to Intel, he concluded.



To: wanna_bmw who wrote (150743)12/3/2001 4:02:26 PM
From: Joseph Pareti  Read Replies (1) | Respond to of 186894
 
great post wanna_bmw.

The following point is intriguing:

Re. Why implement something that at this day and time takes a lot of expense and a loss of yield if the gains achieved are potentially very small? It's no mystery that SOI will be needed eventually to stop certain parasitic effects at smaller geometries, but if they aren't needed now, there is no point investing to bring in the technology early.

why do you think IBM chose SOI for POWER4?