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To: Petz who wrote (64817)12/3/2001 2:05:50 AM
From: Mani1Respond to of 275872
 
John re <<Dan Niles said Intel was having problems increasing P4 output because of testing problems. So you believe that all they need to do is buy more Teradyne testers?>>

I think the problem has to do with through put. Adding further testing stages or wider parameters (temp, freq, etc..) adds to the time required to test each chip. Why did Intel needed to increase testing for each chip? I am sure that is not for the public to know.

Re <<So you believe that all they need to do is buy more Teradyne testers?>>

That is the brute force way of doing it.

Re <<Please explain what a "handler" does.>>

Handler mechanically and thermally deals with the chips. It does not test them, it puts them in testing conditions to be tested. It also sorts them after testing. It is more complicated than it sounds. Here is an example:

deltad.com

Mani