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To: Joe NYC who wrote (150839)	12/3/2001 5:34:17 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Joe, Re: "But if the decoder is in fact half speed and Kap can prove it with software test, the test would be worthwhile, and anybody interested in PC technology should welcome it." Creating a 100% miss scenario will not prove whether the decoders run at half speed or not. The reason is because there is no basis for comparison. What would you say if the Pentium 4 at 2GHz gets, say, the same performance as a Pentium III at 1GHz? The Pentium III happens to have three decoders, while the Pentium 4 only has one, so is the difference in performance due to the number of decoders or the speed of them? Also, I imagine there is a lot of latency in the fetch process, since the Pentium 4 has so many more pipelines than the Pentium III. A continual miss in the instruction stream means that only one instruction at a time goes through the pipeline. Obviously, a 20-stage pipeline will have twice the latency of a 10-stage pipeline. There are plenty of other things involved, which is why I said that Kapkan's application shows the very high penalties of getting near 100% miss rates on the trace cache. However, he'll have no way of knowing what portion of the loss in performance is due to the speed of the decoder, or even if there is a difference in the speed. See what I mean? wbmw