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To: burn2learn who wrote (64947)	12/4/2001 11:49:13 PM
From: fyodor_	Read Replies (1) \| Respond to of 275872

burn2learn, hahah, that's funny. Do you disagree that using hard phase (shift) masks reduce throughput and increase costs? There are quite a few sources that indicate that this is indeed the case, but if you have arguments as to why it is not the case, then I would certainly be interested in hearing them. I've stated several times in the past that I am not a process expert. I have not become one since then ;-). However, I can read. And I do read. Critically and many sources. Now to your questions… Last one first ;-) Do you think advanced process tech comes out of SEMITECH these days? Why or Why not? International SEMATECH (I'm assuming that is what you meant cough) would certainly agree with my assessment that hard PSMs increase overall cost of ownership. You can find reports to this effect on SEMATECH's website (sematech.org). However, I don't know if they have a vested interest [in concluding hard PSMs increasing overall CoO], so I cannot evaluate the objectivity of their conclusions. With regards to any "advanced process tech" coming out of SEMATECH… I would not be the best person to estimate their contribution to semiconductor research. They certainly sponsor a number of talks, forums and seminars - and I would assume that these do contribute in a sum-positive fashion. Since both AMD and Intel are members, I would assume that both these companies feel the same way. whats the downside of PSM on TPT if you can afford to buy many steppers? I have seen estimates of a 10-20% decrease in throughput when using hard phase shift masks + 248nm tools at the 130nm node (as opposed to 193nm tools). I seem to recall a quite significant CoO (masks) increase, but I would assume this varies significantly with volume and hesitate to estimate the impact on Intel. Suffice to say… it sure ain't cheaper ;-). One problem with PSMs is that they deteriorate. This has a negative impact on both yields and throughput (and likely also various chip characteristics influencing bin splits, although I have no data to back this assumption up). With regards to your final question, I have no idea how many (and which) layers Intel would have used the 193nm SVG tools on and how many could have stayed with the old 248nm tools. If you have any information on this, please do enlighten us… -fyo