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To: Joe NYC who wrote (151244)	12/5/2001 6:46:02 PM
From: wanna_bmw	Read Replies (2) \| Respond to of 186894

Jozef, Re: "But the point is, that the clock runs at half of the marketing speed." Remember, that's the point you are trying to make. As of yet, Kap's program hasn't validated that theory. Re: "It's like saying that P4 bus delivers data 4 times per clock cycle. But the clock runs at 100 MHz. No, this is slightly different. While transactions on the P4 bus actually do transfer protocol at 100MHz, it's also true that data transfers at 400MHz. If you understood front side bus protocol, you'd know that transactions come in multiple "phases", the last of which is data. For the Pentium 4, the size of a cache line is 64KB, so when transferring a cache line (which happens most often on the front side bus), it takes 8 data cycles. At 400MHz, this would only take 20ns. A front side bus like on the Pentium III, which operates at 133MHz, would take 60ns - three times longer. Therefore, the bandwidth brings data to the CPU faster. It's not just a clever marketing term. wbmw

To: Joe NYC who wrote (151244)	12/5/2001 7:18:18 PM
From: Timothy Liu	Read Replies (1) \| Respond to of 186894

Joe, Pardon my ignorance on the trace cache, and stubbornness: Here is another one from sandpile.org. On L2 speed and decoder. I would think they mean 'core clock' cycle in this case. The document seems to be pretty updated since it include the 2G P4. sandpile.org ... L1 Cache Speed 1.0x Core Speed L2 Cache Speed 1.0x Core Speed External Bus Speed 100 MHz Quad-Pumped AGTL+ with VTT = VCC Core/Bus Ratio 13.0x, 14.0x, ..., 20.0x ... Instruction Decode 1x IA-32/Cycle Instruction Dispatch 6x µOPs/Cycle 3x µOPs/Cycle Limit imposed by Trace Cache ... My 0.02$ Tim