SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: wanna_bmw who wrote (151372)12/6/2001 4:52:49 PM
From: Elmer  Respond to of 186894
 
Edit: I believe Intel is using another form of local interconnect for their .13u sized caches. It has resulted in a very drastic reduction in cell size, and will probably allow them to build very large caches on some of their processors (6MB of L3 cache on Madison is a good example).

That's why I restricted my comment about Intel to their .18u process. They have stated that their .13u sram cell is the smallest in the industry. This explains why the P3 can have such a tiny die size and still carry 512K L2. I agree, we should expect very large caches from Intel in the future.

EP



To: wanna_bmw who wrote (151372)12/7/2001 6:58:37 PM
From: THE WATSONYOUTH  Respond to of 186894
 
I believe Intel is using another form of local interconnect for their .13u sized caches.

What form of local interconnect do you believe Intel is using for their .13um generation caches?

THE WATSONYOUTH