SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?


To: Joe NYC who wrote (151386)12/6/2001 5:31:25 PM
From: wanna_bmw  Read Replies (1) | Respond to of 186894
 
Joe, Re: "if large chip are of L2 operates at 1/2 of the clock speed, it may mean that of all the various clock speeds on the chips, the largest area may be the one that runs at 1/2 of the marketing speed, and one would have to question if Intel is justified marketing the chips that way."

I disagree with this. Before L2 caches were integrated onto the die, they operated at 1/2 or 1/3 the processor frequency (i.e. the 1GHz Athlon (non-TBird) actually had a 333MHz cache). Back then, the marketed frequency was still that of the on-die logic. I think that even now with integrated cache, it's the frequency of the logic that should be displayed. After subtracting the size of the caches from the Pentium 4 die, I'm sure the area that runs at half the nominal clock is quite small.

One suggestion is maybe marketing the frequency of the logic, and then when cache is mentioned, additionally mention the frequency of the cache. That might give a more accurate description.

wbmw