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To: Joe NYC who wrote (151428)12/6/2001 7:20:42 PM
From: Tenchusatsu  Respond to of 186894
 
Joe, <But P4 has only one that can process one instruction per cycle. That's what the spec says.>

The argument is over whether "per cycle" refers to the main clock or the half-speed clock. Disgruntled former employee Kap claims it's the half-speed clock. He's wrong.

<The L2 latency depends on the speed of the logic and it is completely in the are of the chip which runs at frequency set by the multiplier. You set multiplier to 14 on one, 20 to another. How can the latency be any different in terms of clock cycles? Am I missing something?>

Later steppings of the Willamette core can have longer hard-coded L2 cache latencies. Theoretically, that means a 1.5 GHz P4 bought in late 2000 could actually perform slightly better than a 1.5 GHz P4 bought in late 2001. But the difference is hardly noticeable.

Tenchusatsu