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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Dan3 who wrote (65210)	12/8/2001 1:06:38 AM
From: Dan3	Read Replies (1) \| Respond to of 275872

What would be the value of a merged AMD and SUN? SUN needs a FAB, and a little CPU design support wouldn't hurt - AMD needs compiler design support and enterprise engineering support for things like hot-swap PCI cards and other RAS features. There would appear to be some real synergy possible from a merger of the two companies.

To: Dan3 who wrote (65210)	12/8/2001 1:23:03 AM
From: kapkan4u	Read Replies (2) \| Respond to of 275872

P4/PIII decoders comparison revisited. I asked someone to run a simple loop with a single instruction __asm CLD unrolled 5000 times in the loop. CLD was chosen because it has 4 uops and can only be decoded by one decoder on PIII. This levels the playing field with P4 which has only one decoder to begin with. The loop has to be unrolled at least 3000 times (4 uops * 3000 == 12,000 uops) to overwrite the trace cache which can hold up to 12,000 uops. The results P-III-450MHz 95 M clocks P-III-933MHz 95 M clocks P4-1400MHz 759 M clocks So 1.4GHz P4 performs no faster than 175MHz PIII in this test. Here is the C source to generate the test: #include <stdio.h> int main(int argc, char* argv[]) { int i, iterations, max_lines; if (argc != 4) { printf("invocation error: loop_asm.exe iterations max_lines instruction_string\n"); printf("iterations: number of times the main loop is executed\n"); printf("max_lines: number of repeated instructions_string lines\n"); printf("instruction_string: contains \"__asm instruction __asm instruction ...\"\n"); return 1; } sscanf(argv[1], "%d", &iterations); sscanf(argv[2], "%d", &max_lines); printf("#include <stdlib.h>\n"); printf("#include <stdio.h>\n"); printf("unsigned long x;\n"); printf("#define get_stamp __asm RDTSC __asm mov [x], eax\n"); printf("#define get_count __asm RDTSC __asm sub eax, [x] __asm mov [x], eax\n"); printf("int i;\n"); printf("int main() {\n"); printf("get_stamp;\n"); printf("for( i = 0; i < %d; i++ )\n",iterations); printf("{\n"); for (i = 0; i < max_lines; i++) printf("%s\n", argv[3]); printf("}\n"); printf("get_count;\n"); printf("printf(\"clocks = %%d\\n\", x);\n"); printf("return 0;\n}\n"); return 0; }

To: Dan3 who wrote (65210)	12/8/2001 2:27:18 AM
From: peter_luc	Read Replies (2) \| Respond to of 275872

Dan, thread, can someone comment on this article, please? e-insite.net (Found the link on JC's message board.) "Motorola To Unveil 0.10-Micron Technology Online staff -- Electronic News, 12/3/2001 Motorola Inc. today said it will preview its next-generation 0.10-micron CMOS technology, HiPerMOS 8 (or "HiP8"), and new gate dielectric material this week. Motorola will provide details on its HiP8 platform technology this week at the IEEE International Electron Devices Meeting (IEDM). The technology is expected to complete process certification in December 2002. Motorola, based in Schaumburg, Ill., said HiP8 will allow for a 30 percent reduction in line width over the company’s current HiP7 0.13-micron generation, which in turn will allow for a 50 percent reduction in chip size by increasing gate density and reducing SRAM bitcell area, Motorola said. Motorola expects to manufacture the technology on its fourth generation of copper interconnect. HiP8 supports dual/triple gate oxide, analog, and non-volatile memory modules, the company said, and is also designed to support a range of low power, high performance and silicon on insulator (SOI) applications. The technology is also able to support third party designs and libraries. Motorola also plans to present a paper this week describing the integration of a hafnium oxide gate dielectric into a standard CMOS process. Current leakage is reduced by a factor of 1,000 by switching from silicon dioxide to hafnium oxide, the company said, adding that this development will allow for further shrinking of CMOS devices." Is HiP8 still co-developed by Motorola and AMD? Is this also true for the integration of a hafnium oxide gate dielectric into a standard CMOS process? Would AMD have the right to use this process? Peter