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To: Dan3 who wrote (65213)12/8/2001 1:37:20 AM
From: Dan3Read Replies (1) | Respond to of 275872
 
PC market share numbers:

pcpitstop.com



To: Dan3 who wrote (65213)12/8/2001 1:51:21 AM
From: kapkan4uRead Replies (1) | Respond to of 275872
 
The half speed P4 decoder can't account for this entire monstrosity.

It is possible that P4 implementation is stupid enough to think that there is a dependency on DF between two consecutive CLD instructions trying to blast it to zero. That will create a pipeline bubble all the way to stage 18.

Note that K6-2 executes the same test in just over 30 M clocks (K7 in 17 M clocks -- the beauty of 3 symmetric decoders).

Kap



To: Dan3 who wrote (65213)12/8/2001 2:31:54 AM
From: Joe NYCRead Replies (1) | Respond to of 275872
 
Dan

Trace cache was introduced in P4. The identical result of faster and slower Piii is because the performance is not measured in time, but in processor cycles.

Joe



To: Dan3 who wrote (65213)12/8/2001 10:47:33 AM
From: Charles GrybaRespond to of 275872
 
Dan3, are you sure? I don't think any P3 has trace cache. Some of them got the prefetch.

C


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