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To: Joe NYC who wrote (151727)12/8/2001 5:26:59 AM
From: Tenchusatsu  Respond to of 186894
 
Joe, <It was my assumption until I read Tenchusatsu's posts. I was unaware of the possibility to relax some timing on L2 lookup, sd Tench mentioned.>

I got word that the L2 cache may indeed do its lookups at half speed. However, I don't think the latency is any longer than that of a "full-speed" cache. And the data is still transferred over the L2 bus at full speed.

The decoders still run at full speed, but trace cache runs at half speed. There you go. Trace cache and L2 cache makes up a minority of the chip die area, and it makes no difference whether they run at half speed or full (because of the sequential nature of the transfers), so most of the Pentium 4 still runs at its advertised frequency.

Tenchusatsu



To: Joe NYC who wrote (151727)12/8/2001 11:13:26 AM
From: Elmer  Read Replies (1) | Respond to of 186894
 
If this is what's going on, than I would guess something like this can only happen when new stepping comes online. What do you think?

I think that if cache access turned out to be a significant binsplit limiter Intel could design in a fuse selectable clock tap.

EP