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To: Paul Engel who wrote (152169)	12/12/2001 3:34:53 PM
From: wily	Respond to of 186894

Paul, The 40 nS write pulse is rather long compared to fast synchronous DRAMs or DDR - but it is quite a bit faster than Flash write timing (a rather slow process that can take milliseconds). Latency generally refers to the delays associated with reading the first - or the first in a stream - memory location including address generation, address loading, (RAS/CAS assertion, etc.) - that is - how long does it take to get the data once the data is requested. So, given that OUM is nonvolatile and therefore avoids a lot of operations that contribute to DRAM latency, how fast a write pulse would be needed for its latency to be competitive with DRAM? I realize this is probably a moving target but, if you could ballpark this for me... Here's another one: If the write pulse current for OUM is considerably less than that for DRAM (and I don't know for sure that it is -- but IF it is), would this allow for a proportionally wider bus, and hence a higher data rate? And finally, would latency be reduced a lot by putting OUM on-chip? Thanks mucho, wily