To: Bilow who wrote (80412 ) 12/22/2001 9:24:35 AM From: mikea388 Read Replies (1) | Respond to of 93625 Rambus Signaling Technologies Overview Yellowstone Signaling Technology Rambus announced its newest signaling technology, code named "Yellowstone" at the Rambus Developer Forum in October 2001. Yellowstone's bi-directional differential signaling technology offers a high-performance, low-power, and cost-effective solution for getting bandwidth on and off chip. Yellowstone uses Differential Rambus Signaling Levels (DRSL) with ultra-low 200mV signal swings from 1.0 to 1.2V. DRSL enables low power operation and scalability for future lower voltage processes. Whether connecting to memory devices or between system ASICs. Yellowstone operates at Octal Data Rates (ODR), transferring 8 bits of data per clock. ODR enables 3.2GHz data rates with a 400MHz clock and provides a scalable path to over 6.4GHz as bandwidth needs increase. RaSer: Rambus Serial Link Technology To address the communications market with a specialized point-to-point signaling technology, Rambus introduced RaSer, a SerDes (Serializer/Deserializer) cell technology. Rambus' RaSer Cell is available as a single, dual or quad cell, and allows a lower cost, simpler backplane connection with 25% greater performance at lower power than alternative stand-alone SerDes components. The Rambus 3.125Gbps Quad SerDes Cell, for example, can support the 10Gbps full-duplex data rate popular in network line cards supporting OC48, OC192 and higher data rates over 30 inches of interconnect. RaSer cells are offered as complete system solutions for ASIC and ASSP designs. They contain serializer/deserializer, transmitter, receiver and clock recovery circuitry. The RaSer cell eliminates the need for standalone SerDes components and offers the ability to ensure interoperability across different silicon vendors and process technologies through fully characterized macrocells available in popular ASIC and foundry technologies. RDRAM Memory In 1992, Rambus introduced its flagship technology, Rambus Signaling Level (RSL) technology. RSL provided the semiconductor manufacturers with 10 times the bandwidth, or 500MHz, than was used in PCs at that time. The innovative signaling technology transferred one bit of information per clock edge. Over time, RSL was improved to operate at 800MHz on a long channel (with modules) and 1066MHz on a short channel (devices soldered to the motherboard). Today, the RSL roadmap looks out to 1200MHz. Designed using Rambus Signaling Levels (RSL), RDRAM devices provide designers with operating speeds significantly faster than currently available DRAM devices. RDRAM devices provide systems with 16MB to 2GB of memory capacity at speeds of up to 1066MHz. The RDRAM Channel achieves its high-speed through several innovative techniques that include separate control and address buses, highly efficient protocol, low voltage signaling and precise clocking to minimize skew between clock and data lines. Rambus ASIC Cell The RAC cell is an easy-to-implement library of interface circuitry and logic necessary to provide the designer full control over the RDRAM Channel. It's flexible enough to used for applications ranging from simple memory controllers, complex multi-port memory controllers, or as a communications path for high-speed chip-to-chip interfaces without forcing any particular design implementations RAC cells are available across a wide selection of different processes, vendors, and design rules. This interconnect technology is based on leading-edge CMOS processes for easy integration into controller designs.