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To: whortso who wrote (66324)	12/27/2001 4:25:08 PM
From: pgerassi	Respond to of 275872

Dear Whortso: You missed the point, as usual! Each pin takes a certain amount of die area, 0.1mm2 for example. The wire bonders, or flip chip bonders which are more dense (more pins per a given die area), need a certain area to make sure they can attach the wire that goes from the die to the lead frame pin. This is not allowed to be any smaller or your error rate goes up fast (with 900+ pins even a 0.1% error rate per pin would reject 60% of the dies just because a wire went astray). Thus, a chip must have an area of 90mm2 just to hold the wire bond pads. It can't be any smaller than that no matter how small the process used to make transistors. With a 0.35u process, you can get 17 million transistors on a flip chip. If you use less, well some of the die area just goes unused (blank). With a 0.25u process, you can get 34 million transistors and with 0.18u you get 68 million transistors. This goes up as the process gets smaller. So many use this as a constraint on the process required. If they need only 8.5 million transistors and the 0.50u process is fast enough, they use that for the 900+ pin NB. If they need to use a smaller process for speed purposes, they just have a blank area for those pads (the pads are added at the highest metalization area, so transistors can go underneath on most chips in use today). That blank die area is free to be used in any design for more logic/memory on that NB. That is just what Micron proposed with Mamba, use 0.18u and the blank area could hold 8MB (64 megabits) of ESDRAM (embedded SDRAM) to be used as a L3 cache. The other reason to use the biggest process is that it is fully depreciated and thus can be done at the lowest cost per given die area. If you can't understand this, you must be playacting as you were a dunce. Pete