Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Saturn V who wrote (153755)	1/4/2002 2:04:21 PM
From: Elmer	Read Replies (2) \| Respond to of 186894

"If you look today on a microprocessor, a Pentium 4 has about 42 million transistors. That means, on a 300 millimeter wafer, we have about 20 billion transistors, and they're all supposed to work," Marcyk said. I think Intel just told us they'll have ~475 whole Northwood die on a 12" wafer... If they get 300 good die and the wafer costs $3000 that makes a die cost of $10. AMD is in deeeeep dodo. EP

To: Saturn V who wrote (153755)	1/4/2002 3:46:13 PM
From: Proud_Infidel	Respond to of 186894

Intel readies road map for billion-transistor processors By David Lammers EE Times (01/04/02 10:29 a.m. EST) HILLSBORO, Ore. — Intel Corp. expects its microprocessors to hit one-billion transistors by 2007, up from 42 million in the current Pentium 4, said Gerry Marcyk, director of components research at Intel's development facility. While process technology generally moves forward in two-year cycles — with shifts to 90-nanometer lithography design rules expected in 2003, to 65 nm in 2005, then to 45 nm in 2007 — packaging will have to hustle to keep up the pace, Marcyk said. The chip industry doesn't pay enough attention to packaging, and putting advanced transistor technology into old packaging "is like putting a Formula One engine in a Yugo body," Marcyk said. Intel will move from its plastic bumped organic land grid array package to a bumpless package with built-up layers. By embedding a die inside the package and getting rid of the bumps, the package thins down to the thinness of a dime. A thinner package allows faster speeds and halves the number of copper layers in the package, he said. Intel calls its bumpless package the BBUL, for bumpless build-up layers, and expects it to come into use in the second half of the decade. BBUL would support multiple chips, such as two processors and supporting silicon. Getting to a terahertz-class transistor this decade will require some radical shifts in process technology, Marcyk said, including fully depleted silicon-on-insulator (FD-SOI), and a new gate oxide material. FD-SOI places an ultra-thin layer of silicon on top of an insulating substrate, and will help to "completely turn off every atom" in a transistor that is not in use, he said. Replacing today's nitrided silicon oxide as the gate oxide with a new — and as yet publicly unidentified — gate insulator will require atomic layer deposition tools, rather than the chemical vapor deposition used today. But the upside of the changes is that the new insulation material will reduce current leakage at the gate by three orders of magnitude, Marcyk said. Cutting leakage current and reducing operating voltage are two important "knobs" that process technologists must turn in order to reduce power consumption in microprocessors. Lithography remains a challenge as well, though Intel is banking on extreme ultraviolet lithography to replace 157-nm scanners in the second half of the decade. Marcyk said Intel is not interested in electron-beam projection lithography because as devices get smaller, the e-beam approach gets slower. But he acknowledged that Intel is looking at some other highly speculative forms of lithography in the lab.