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To: Saturn V who wrote (153856)1/5/2002 10:39:25 AM
From: Dan3  Respond to of 186894
 
Re: As an Intel shareholder I hope that my pessimism is unwarranted.

Infineon doesn't seem to have any trouble with the 300mm wafers they've been using in Dresden since 1999. I realize that SDRAM is less difficult CPU/logic, but it's just about the only data, so far, on commodity mass production 300mm FABs.

Aren't a few 300mm lines up at some of the Taiwan FABs, as well?



To: Saturn V who wrote (153856)1/5/2002 10:54:36 AM
From: semiconeng  Respond to of 186894
 
I am glad that you are so confident. However my experience shows that continuous scaling and shrinking brings new problems to light which were not considered to be an issue historically . Thus the process parameters which affect these `unrecognized problems' are not monitored. And sometimes such `hidden problems' ( manifested as yield and reliability problems ) frequently lurk on the edge of wafers, and go ignored. A Wafer Size Increase thus suddenly expose these problems.

---My hands on experience doesn't seem to bear out your conclusions. Modern KLA and ATI Defect Inspection, coupled with Chromatography Defect Analysis, can identify the root cause of most defects. Along with High Power Scanning Electron Microscope Topography, and Cross Section Peel Back SEM Techniques, Development Engineers should be able to identify most, if not all of the "unrecognized" or "Hidden" problems before a Fab starts High Volume Manufacturing.

---The problems as you describe, are usually identified during development, and the Process would certainly not be deemed manufacturable if those conditions existed. I don't know who you work for, but If we have bad yield on the edge die, baby you better BELIEVE my butts in a Task Force Mode until it's solved.

For example both you and Elmer referred to poorer bin splits and reliability on the edges. Enlarging the wafer obviously will make these issues worse. However these problems are not fundamental, and once recognized, they are solved by diligent engineering. So my model is that the effective yield will not reach the potential value for six to nine months.

---Right, and just what do you think they're doing right now in Hillsborough?? Sleeping?? Intel has been in development on 300mm P1260 for longer than the time you describe, so therefore based on your logic, all issue should be solved...... TAAAAA DAAAAA.....

As an Intel shareholder I hope that my pessimism is unwarranted.

---No offense, but..... I know it's unwarranted. Believe it, or not.

:-)

Semi



To: Saturn V who wrote (153856)1/5/2002 11:23:04 AM
From: Elmer  Respond to of 186894
 
However these problems are not fundamental, and once recognized, they are solved by diligent engineering. So my model is that the effective yield will not reach the potential value for six to nine months.

It wouldn't surprise me if you're right. In fact it would surprise me if you aren't but 6-9 months isn't all that long.

EP