<font color=blue>Platform Conference details
http://www.platformconference.com/attendeeinfo-agenda.htm
Platform Conference is just over two weeks away, and we're pleased to announce that a detailed agenda is now available online. For your convenience we've included it here below.
Please be sure to check out all the details and pre-register online today at platformconference.com .. With over 50 sessions to choose from, it pays to bring other members of your team. Be sure to take advantage of our discounted group rates.
We look forward to seeing you there!
In case you missed the early registration discounts...we've extended them through this Friday! Be sure to register now while you're thinking about it. Save $200 off Individual Registration and over $450 per person on Group Registrations.
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Platform Conference Agenda
Wednesday, January 23, 2002
9:00am - 10:00am
Keynote
Welcome Address
Bert McComas - Founder and Principal Analyst
InQuest Market Research
Delivering Total Connectivity
Richard Brown - Director of Marketing
VIA Technologies
Next Generation Performance Computing
Ed Ellett - Vice President, Server and Workstation Marketing, Computation Products Group
AMD
10:30am - 11:20am
Power Panel Discussions
Ballroom 1 Ballroom 2
What to Sell When MHz Doesn't Matter? The Interconnect Conundrum: The Future Beyond PCI
Moderator: Jon Peddie - President, Jon Peddie Research
Moderator: Nick Stam - Senior Technical Director, PC Magazine Labs and ExtremeTech
Panelists: AMD, VIA, MIPS Technologies, Equator Technologies, National Semiconductor
Panelists: ServerWorks, API Networks, Tundra, Primarion
11:30am - 12:20am
Power Panels
Ballroom 1 Ballroom 2
Networking, Clustering and Storage: What Standards Will Dominate? Directions for DDR
Moderator: Bert McComas - Principal Analyst, InQuest Market Research
Moderator: Sherry Garber - Vice President, Semico Research
Panelists: Broadcom, Adaptec, IBM, NEC, Mellanox
Panelists: Kentron Technologies, Micron, Infineon, Denali Software
1:30pm - 2:20pm
Breakout Sessions
Ballroom 1 Ballroom 2
Understanding Commercial Platform Solutions
The mystique of commercial platform requirements will be decloaked in this session. Manageability, health monitoring, platform certifications and specific BIOS requirements will be examined and explained. Intended for developers of bid-boxes and commercial system suppliers, this session will address how to understand and meet the most common requirements found on a platform bid request. Terms like WMI, DMI, SNMP,WHIIG, CIM and WHQL will all be addressed.
Presented by: AMD
Advanced P4 SMA Chipset for Mainstream Commercial PC market
With corporate and commercial IT budgets shrinking, a need for “cost effective” PC systems has arisen. In the past “cost effective” has also meant a sacrifice in performance, especially with mainstream business software. With the introduction of the first SMA Pentium 4 chipset to support DDR memory and the recent price shifts of the Pentium 4 CPU, cost effective but slow are no longer synonymous with each other. In this presentation, we will introduce this SMA Pentium 4 chipset for the mainstream corporate and commercial PC marketplace. Topics include an overview of the Pentium 4 System Memory Architecture, including the internal chipset architecture, data path, and system partition, and the major benefits in the mainstream corporate and commercial PC.
Presented by: VIA Technologies
Ballroom 3 Ballroom 4
DDR333/PC2700 and Beyond -- The New Standard for Main Memory
DDR SDRAM has achieved all of the goals that were established for 2001 and will emerge as the dominant next-generation memory technology in 2002 for high-performance desktop PCs, servers, and notebooks. The acceptance of DDR as the industry's next main memory standard demands that DDR move beyond DDR266/PC2100, to DDR333/PC2700 and beyond. This session will look at the status of DDR333/PC2700 and higher-speed standards, and explore the system assumptions. In addition, system simulation and measured data will be presented; and component and module variations will be discussed.
Presented by: Micron
3.2+ GB/s Memory Systems - Choices for the Future
With processor speeds rapidly approaching 3GHz, system designers must select memory technologies which can effectively meet memory bandwidth requirements. Presentation will provide a comparative analysis of the system level memory implementation choices faced by designers. Topics will include performance, space, cost, and reliability. Multiple memory technologies coexist in the market today allowing data driven comparisons to be made.
Presented by: Rambus Inc.
3:00pm - 3:50pm
Breakout Sessions
Ballroom 1 Ballroom 2
The Changing Face of Servers: Insights for Developers of IA Server Platforms
This session uncovers the issues and opportunities for IA-based servers in 2002 - including platform trends, market requirements and design challenges. Strategies will be influenced by new form factor requirements, new integration and partitioning options, new high-speed I/O technologies, 64-bit computing, enhanced connectivity capabilities and emerging software applications. All of these will impact how the industry will architect servers. This session will also take a detailed look at key technology initiatives and how they will impact future IA server platform designs.
Presented by: ServerWorks
VIA C3 Eden ESP for advanced IA application
This session will examine the trends and market opportunities for Internet Appliance platforms. Understand the silicon building blocks, technologies and architectures VIA is developing for designers of Internet Appliance platforms. Included will be a discussion of advanced microprocessor features, performance, power consumptions as well as motherboard form factors and turn-key reference designs.
Presented by: VIA Technologies
Ballroom 3 Ballroom 4
Instant-On and XIP with SyncFlash Memory
Those interested in high-performance embedded computing products may want to check out what SyncFlash memory has to offer. SyncFlash memory is a nonvolatile device with a 100 MHz SDRAM read-compatible interface--which means that for the first time in main memory architecture, SDRAM and Flash memory can reside on the same bus. A hardware proof-of-concept demonstration of instant-on and XIP applications will be provided, and examples of implementation architectures will be discussed.
Presented by: Micron
A New Display Solution for the Integrated Graphics Accelerator Market
This proposal describes a new, easy, and low cost DVI / TV Out solution for an optional AGP DVI/TV Out riser card targeted for the integrated graphics accelerator core logic market. This proposal also allows other possible display features to be incorporated if desired in the future. This proposal will describe some of the current issues with the integrated graphics accelerator core logic market in growing the stagnant DVI/TV Out market. It will also describe in detail the issues with one possible idea that is currently being discussed in the market as a possible solution. The proposal will then explain in detail this new, easy, and low cost solution and show the advantages it has to the market. It will show some of the current boards and systems that implement this solution. A list of some of the leading motherboard and system manufacturers that have already announced plans to go into production with this solution will be included.
Presented by: NVIDIA
4:00pm - 4:50pm
Breakout Sessions
Ballroom 1 Ballroom 2
Memory Solutions for Mobile Platforms
Longer battery life, moving picture capability, and small form factors are essential requirements for mobile platforms. 3G phones, PDA, and convergence devices are driving the requirements for low voltage, low power, and multi-chip packaged memories. Samsung, the leader in memory technology is well positioned to service these needs with multitude of products. 1.8V DRAM will be in volume production in 2002 with 1.0V DRAM expected to be in production by 2005. World's first 1.8V NAND FLASH was introduced by Samsung this year along with 32Mb Low Power SRAM. In this paper, we will examine memory needs for the mobile platforms and Samsung's memory solutions.
Presented by: Samsung
Hi-Speed DDR333 DRAM Sub-System Design
With the introduction of the DDR333 memory, the newer and the faster speed grade of industry standard DDR SDRAM family, the quality of the DRAM subsystem design become even more critical in the overall system stability and performance. In this presentation, results of the extensive engineering effort by VIA and top DRAM companies will be presented. Specific topics include: dram sub-system topology study and recommendations, advances in DDR333 module design, DDR 333 System solutions.
Presented by: VIA Technologies
Ballroom 3 Ballroom 4
Introducing -- RLDRAM Architecture
Reduced latency DRAM (RLDRAM) is designed to meet the needs ofhigh-bandwidth, high-speed, latency-sensitive applications such as network switches, routers, and cache in high-speed servers. Co-developed by Micron Technology and Infineon, this innovative technology bridges the cost/performance gap between SRAM and DRAM. Micron's RLDRAM session will provide an informative introduction to its unique internal architecture and discuss the design considerations behind its development.
Presented by: Micron
Mobile AGP Package (MAP) - The Packaging option for the next generation of notebooks
This new technology packs all the features of desktop AGP cards, including up to 64MB of memory, onto a single-chip solution and is designed to support multiple generations of graphics technology. In addition to reducing the space required for the graphics subsystem, MAP reduces the complexity of future notebook motherboard designs. This translates into reduced development costs and faster design verification for the OEMs and faster access to new technologies for notebook users. Using standard Ball Grid Array (BGA) memories from a variety of vendors, the cost of MAP can leverage the economies of scale of the commodity memory market. With MAP OEMs are able to utilize a standard AGP interface which will allow for flexible and scalable technologies to be incorporated into a new generation of notebook designs.
Presented by: NVIDIA
5:00pm - 5:50pm
Breakout Sessions
Ballroom 1 Ballroom 2
Small Form Factor Design Considerations
This technical session will address the challenges associated with developing a high performance, small form factor performance PC. Thermal design considerations, acoustic challenges and heat sink solutions are major topics that will be covered. Solutions that apply to both custom and standard chassis sizes will be addressed.
Presented by: AMD
DRAM Market: Drivers, Opportunities and Some Cautions
The DRAM market never moves in small increments. Diversity of DRAM types is increasing as various end applications demand different types of DRAM. Will the DRAM market continue to resemble a roller coaster ride? Is the direction of the market down or up? How do end products affect all of this? Discussion will include information on DRAM demand for various end applications. Forecast on DRAM market direction. Where are the opportunities and what are the risks for some of those opportunities.
Presented by: Semico Research
Ballroom 3 Ballroom 4
DRAM Memory: Low Power, at What Cost?
The memory requirements for higher densities and increased speeds have brought attention to the memory subsystems' power consumption. Infineon's presentation will explore the history and trends of DRAMs, as it relates to power consumption, the various design techniques, and its trade-offs to lower the overall power budget.
Presented by: Infineon Technologies
Towards the Fanless PC
It's time for the PC to please shut up! The availability of high bandwidth Internet connections and the presence of music and video file formats has enabled a wealth of new applications for the PC as a home entertainment center. However, the noise generated by personal computers reduces the enjoyment of these media and keeps the PC locked in a side room away from the family living space. Let's look at the sources of noise and lay out a roadmap for the Fanless PC as a true, quiet home appliance.
Presented by: Transmeta
Thursday, January 24, 2002
9:00am - 9:50am
Breakout Sessions
Ballroom 1 Ballroom 2
Hi-Speed DDR333 DRAM Sub-System Design
With the introduction of the DDR333 memory, the newer and the faster speed grade of industry standard DDR SDRAM family, the quality of the DRAM subsystem design become even more critical in the overall system stability and performance. In this presentation, results of the extensive engineering effort by VIA and top DRAM companies will be presented. Specific topics include: dram sub-system topology study and recommendations, advances in DDR333 module design, DDR 333 System solutions.
Presented by: VIA Technologies
Understanding Performance
The True Performance Initiative, driven by AMD, is an educational initiative to determine the most appropriate measure for PC performance and to assist customers in understanding the benefits of PC performance. Historically, processor frequency has been a good proxy for performance. However, with the recent divergence of the internal architectures of x86-compatibleprocessors, frequency is no longer a good proxy. Future processor and platform innovations will further complicate performance positioning.
Presented by: AMD
Ballroom 3 Ballroom 4
The HyperTransport Physical Interface
Presented by: Dolphin
Part I: HyperTransport Technology: A Tutorial
HyperTransport solves a number of problems seen in traditional I/O interconnect schemes. This tutorial session presents a look at the problems, and introduces the major features of the HyperTransport solution. General HyperTransport topics discussed include system architecture variants, scalability, and device configuration. Included in the coverage of HyperTransport transactions are the concepts of virtual channels and IO streams, and descriptions of packet types, flow control, electrical signals, and error handling.
Presented by: Mindshare
10:00am - 10:50am
Breakout Sessions
Ballroom 1 Ballroom 2
Evaluating RLDRAM for Your Solution
Reduced latency DRAM (RLDRAM) has been co-developed by Infineon and Micron Technology with the input from network industry leaders. This presentation will enable you to evaluate RLDRAM, and compare and contrast to other memory technologies. It will also allow you to make an informed choice for your high-speed memory architecture.
Presented by: Infineon Technologies
QBM Alliance - Working together to deliver QBM200/533 memory solutions in 2002
Kentron Technologies and other members of the QBM Alliance will discuss the status of the launch of new platforms utilizing the Quad Band Memory (QBM) technology. The discussions will include an update of the technology as well as presentations covering new switches and PLLs that have been developed to help make QBM 200/400 a reality in Q1, 2002. The road to 6.4GB/sec and beyond will be presented as part of the QBM product roadmap through 2005.
Presented by: QBM Alliance
Ballroom 3 Ballroom 4
HyperTransport and Infiniband: The Complete High Bandwidth I/O Solution
HyperTransport technology and InfiniBand Architecture are two emerging I/O standards, targeted to meet the needs of servers and data centers. How do these two new standards relate to each other? What needs do they fulfill? Eric Krause from AMD looks at both technologies and answers this question in a document, "HyperTransport Technology and InfiniBand Architecture: The Complete High Bandwidth I/O Solution." This session presents a high-level analysis of both interfaces and how they might impact the future of platform architectures.
Presented by: AMD
Part II: HyperTransport Technology: A Tutorial
HyperTransport solves a number of problems seen in traditional I/O interconnect schemes. This tutorial session presents a look at the problems, and introduces the major features of the HyperTransport solution. General HyperTransport topics discussed include system architecture variants, scalability, and device configuration. Included in the coverage of HyperTransport transactions are the concepts of virtual channels and IO streams, and descriptions of packet types, flow control, electrical signals, and error handling.
Presented by: Mindshare
11:00am - 11:50am
Breakout Sessions
Ballroom 1 Ballroom 2
QDR II/DDRII SRAM -- The Next Level of Performance
Very high-speed, high-bandwidth memory solutions are essential to meeting the switching and data throughput requirements of the networking industry. QDR/DDR SRAM meets these requirements and more. The QDR family of SRAM devices was co-developed by major memory manufacturers to ensure compatibility and guarantee availability. Members of the co-development team will present a detailed technical overview of QDRII and DDRII SRAM technologies, including features and benefits, implementation strategies, clocking strategies, density migration, and product road maps.
Presented by: QDR Co-Development Team
Part I: Addressing Today's System Interface Requirements with HyperTransport Technology
Altera offers a comprehensive solution including devices that offer support for high-speed I/O and MegaCore intellectual property for various protocols to address the interoperability requirements of high-speed system designers. This session will highlight the APEX II device’s 1-Gbps True-LVDS solution and embedded SERDES unique to Altera’s PLDs. Additionally, it will provide an overview of Altera’s 8-Gbps Hypertransport solution and Altera’s revolutionary Atlantic interface.
Presented by: Altera
Ballroom 3 Ballroom 4
Part I: Managing Isochronous Data Streams on a HyperTransport I/O Link
Presented by: NVIDIA
HyperTransport Based Security Processing
Security processors are used to offload compute intensive number crunching associated with security protocol processing like SSL and IPsec. As application bandwidth requirements of systems enter multi-gigabit performance ranges, traditional look aside (co-processor) buses like PCI and even PCI-X are becoming the bottle-neck in systems. Cavium Networks has integrated the high performance HyperTransport interface to overcome the I/O bottleneck. In addition to high performance, HyperTransport provides NITROX with point-to-point robust electricals, PCI software transparency and popularity with emerging network processors.
Presented by: Cavium
1:00pm - 1:50pm
Breakout Sessions
Ballroom 1 Ballroom 2
What You Need to Know: Bare Die Design Guidelines
The use of bare die and advanced assembly techniques that produce system-in-a-package (SIP) or multi-chip-modules (MCMs) is clearly on the rise. This presentation focuses on the use of bare die in an SIP/MCM configuration versus individually packaged components. It discusses FIT rates and DPM as they relate to system costs and delineates when KGD processing is worth paying for. It also discusses available memory types and how they are tested at wafer level. This is a great opportunity to gain practical insights into the cost effectiveness, performance enhancements, and board savings that can be realized using bare die in MCM-type solutions.
Presented by: Chip Supply/Micron
A Trend to Future Platform and Chipset Integration - Wireless & High Speed Links Technologies
To strengthen the overall PC performance, PC platform has to integrate more hardware features allow new applications for end users. Many new wireless standard and new high speed links would become available in the near and midterm future. Chipset integration would be one of the path to bring down the cost. This section will discuss some of the features, benefits and some of problems for integration.
Presented by: ALi
Ballroom 3 Ballroom 4
Delivering Gigahertz Multiprocessors with HyperTransport Support
Broadcom is shipping BCM1250 - a MIPS-64 integrated multiprocessor with HyperTransport. Learn more about the Broadcom's SiByte family of processors including the recently announced BCM1125 and how system designers can achieve improved I/O bandwidth and scalability with HyperTransport.
Presented by: Broadcom
Part II: Overview of Virtex-II family of FPGAs with HyperTransport
With the continuous push for higher bandwidth, the HyperTransport interface standard has emerged as one of the key interfaces that can solve the I/O bottleneck issue. Using the high performance Virtex(tm)-II platform FPGA feature set, Xilinx provides a comprehensive offering of high-speed system interface LogiCORE(tm) intellectual properties in its Platform FPGA SystemIO solutions to support the new emerging standards. This session will highlight the Virtex-II FPGA feature set that enables designers to meet their high-speed design requirements, and provide an overview of Xilinx Hypertransport solution.
Presented by: Xilinx
2:00pm - 2:50pm
Breakout Sessions
Ballroom 1 Ballroom 2
JAZiO: I/O Switching Technology for High Performance
JAZiO I/O switching technology provides a roadmap for the highest per pin bandwidth for parallel, inter-chip communication. JAZiO is the only technology with differential sensing with only one pin per data bit. Results from the evaluation of the first-ever JAZiO Demonstration Chip will verify the effectiveness of this novel technology.
Presented by: JAZiO
Gigabit to the Desktop
This session will focus on the tangible, real-world benefits of deploying a pervasive Gigabit Ethernet solution in an enterprise business computing context. Key topics will include a discussion of Gigabit's impact on specific client/server and business productivity application scenarios; an analysis of the relationship between client PC performance and Gigabit throughput; and an introduction to the CSA's application-level testing methodology. Attendees will walk away with a better understanding of why a pervasive Gigabit solution is the right platform for today's high-performance PCs.
Presented by: CSA Research
Ballroom 3 Ballroom 4
Delivering Next Generation Packet Processing: Integrated Multiprocessor with HyperTransport Technology
Packet processing requires very high performance in both the CPU and I/O subsystems. The PMC-Sierra RM9000x2 integrates dual gigahertz CPU cores and a high bandwidth HyperTransport interface to address these requirements. This presentation follows the path of a packet over the HyperTransport interface into the RM9000x2, and illustrates how the sophisticated feature set of the RM9000x2 quickly and efficiently processes the packet.
Presented by: PMC-Sierra
Enabling high performance IC designs with HyperTransport IP blocks from GDA Technologies Inc.
High bandwidth applications of today and tomorrow need IC designs incorporating Hypertransport technology. This presentation outlines the various Hypertransport IP offerings, design and verification techniques, integration challenges with the Physical layer blocks and board design consideration to get your IC design right and on time.
Presented by: GDA Technologies |
