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To: Charles Gryba who wrote (154648)1/10/2002 11:41:28 AM
From: wanna_bmw  Respond to of 186894
 
Constantine, Re: "what I am getting at is that if Intel is correct, what's to prevent everyone else from switching wafers to FD wafers when they become available."

Nothing is to stop AMD from doing the same, but there are going to be many differences in processing between the two, and Intel seems to currently be ahead in finding solutions for potential problems. What I'm trying to say is that there is more to it than simply buying the right wafers.

wbmw



To: Charles Gryba who wrote (154648)1/10/2002 12:14:13 PM
From: fingolfen  Respond to of 186894
 
wbmw, quick question for you or anyone else who knows. Am I to assume that the difference between FD and PD is in the wafer manufacturing or are there other changes that have to be made to produce cpus for those two different kinds of SOI? Basically, what I am getting at is that if Intel is correct, what's to prevent everyone else from switching wafers to FD wafers when they become available.

There are lots of ways to get a FD SOI wafer, but the most efficient for a company like Intel would be to buy it from a silicon vendor.

The bottom line is nothing is preventing the world+dog from going with FD SOI, and by publishing all of these papers, I honestly think Intel is trying to drum up industry support. If, however, you look at the paper w-bmw posted, this is a scaled up version of a "Terrahertz" transistor. It has all of the same hallmarks: FD SOI, raised S/D, and high-K gate. FD SOI by itself has several disadvantages. High-K gate by itself is nice, but it's only one component to increase performance. Throw in raised S/D and you get the hat trick... so to speak.

Even though the dimensions in this paper are equivalent to the 90nm node... I'm not sure that you'll see the three together until the 65nm node...