Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: wanna_bmw who wrote (155129)	1/12/2002 11:31:46 PM
From: milo_morai	Read Replies (1) \| Respond to of 186894

Wanna, the Memory bus doesn't have to track FSB. Case in point New ASUS MB 333Mhz DDR memory and still has FSB of 266/200 tbreak.com

To: wanna_bmw who wrote (155129)	1/12/2002 11:36:38 PM
From: Charles Gryba	Respond to of 186894

wbmw, re:"I was under the impression that the memory bus increases at the same speed as the front side bus. Would this not give extra bandwidth to both areas, and eliminate the bottleneck you are describing?" Yes and no. For example, The P4 has a 4x100 bus but it can be run with all kinds of chipsets/memory. So even though the bus stays the same, the chipset/memory makes a big difference. So what I am saying is that the current high scores for the P4 are from dual-channel memory which can feed its high bandwidth. The athlon lacks both the dual channel and the high fsb, so it has more potential gains. That's all I am saying. re: "any resources you put onto a project like this, you would be subtracting from Hammer development. If you ran AMD, you would be pushing out Hammer schedule even farther, just to compete with Intel at the front side bus. But let me ask you: once you pull people from the Hammer team to create a chipset with a 200MHz Athlon bus, would you pull more people to improve the memory bandwidth, and more people to do a reference design, and more people to handle electrical issues, and more people for validation, etc?" You are making the assumption that AMD is strapped for engineering talent. I don't know the answer. re:"Oh, and also, if you start now, you might be able to get such a project out by 2004. Yes, it does take that long to start a project like that from scratch. Unless you are trying to prove that in 2000, AMD previously anticipated that Intel will have caught up to them, and they pushed for a chipset with 200MHz Athlon bus at that time? I am just wondering, Constantine, because your theories don't seem to add up." I never said they started now. Since the EV6 was designed as a 200FSB from day 1 I guess some preliminary work was done 4-5 years ago. They could have started the upgrade to 200 fsv when it became known that the P4 had such a high frequency bus. C