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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: TigerPaw who wrote (142156)	1/26/2002 7:03:19 AM
From: combjelly	Read Replies (1) \| Respond to of 1583404

"That should really help speed, right?" Yep, for several reasons. One of the most important is latency. Currently, when there is a memory request, it goes through the circuitry on the processor, formatted for the bus protocol, through the buffers, across the traces, into the recievers on the north bridge, formatted for memory bus protocol, across some more traces, to the memory chips. With the memory controller on the processor itself, several of these steps can be eliminated. While it doesn't amount to a whole lot, it can shave some time off. In addition, because the processor knows more about the data it wants than a north bridge would, it could potentially overlap some of the steps it has to do, shaving even some more time off of each request. And we know that latency is a big factor for many operations. A good example, look at the P4 on a i850 chipset and an i845D. The memory bandwidth for the i850 is 3.2GBytes/sec and the i845D is 2.1GBytes per second. Now since the P4 is really sensitive to bandwidth, you would expect the i845D system to be hurting really bad. But it is not the case. In several cases, the i845D is faster than the i850. In fact, it only loses out on things that are straight memory bandwidth limited, and even then it is pretty close. The biggest difference? The Rambus memory on the i850 motherboards have significantly more latency than the DDR memory of the i845D. Now certainly if the i845D had more bandwidth the P4 could use it, but the few clock cycles of less latency can usually more than compensate for the 30% or so less bandwidth. The downsides are that it makes the processor more difficult to design, and it locks you into a particular type of memory technology. If Intel had done that with the P4, then it would have been stuck with Rambus memory and they would have to change the chip design to use SDRAM or DDR.