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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: combjelly who wrote (157021)	1/27/2002 1:42:14 PM
From: wanna_bmw	Read Replies (2) \| Respond to of 186894

Combjelly, Re: "Well, no. Just that it is difficult to design around something for which the specifications don't exist. But you probably know that too. Are you saying that AMD should have delayed the Hammer tapeout so that DDRII could be incorporated?" I have first hand experience of how difficult it is to design around something whose specifications either don't exist, or are incomplete. But that hasn't ever stopped me; nor has it stopped SiS, ALi, and others, who have designed chipsets around DDR333, even though the specs were unfinished by JEDEC. I would not suggest that AMD do something like delay Hammer to implement every new memory technology that comes out. Then they would never tape out. Rather, I am only illustrating the inherent trade offs to including an integrated memory controller. Despite the belief of some people that integrating the memory controller is the greatest technology since the transistor, there are downsides that can impact development later in the future. Intel has had the opportunity to integrate the memory controller since their Timna design, and had it not been for the fact that Rambus was becoming an expensive and unpopular technology, Intel would have been first to market with it. However, they had their own reasons to not implement that technology in other cores. The most obvious reason is that they want the flexibility of other memory standards by way of the chipset, but there could be many others that we don't even know about. Re: "Does the industry need the higher bandwidth? For processors, it isn't as useful as lower latency. Look at the P4, an i845D system is almost as fast as an i850 system despite the 1/3 lower bandwidth." Obviously, bandwidth and latency each benefit different kinds of applications. With the Pentium 4, it seems that the "sweet spot" for bandwidth exists between 2.1GB/s and 2.7GB/s. Within this range, memory bandwidth can satisfy the majority of applications. However, this is for Pentium 4 processors operating in the range of 1.7-2.0GHz. When these frequency doubles, which is bound to happen in the next 18-24 months, then memory bandwidth requirements are obviously going to be much higher. Latency doesn't much improve from generation to generation. By integrating the memory controller, AMD has bought themselves a one-time performance gain, but with each new memory standard, they are going to have to design an entirely new CPU. Just think about the platform requirements of that, too. With changes in the CPU, system level bugs will find a way of appearing. Validation will have to increase to ensure operation with currently released chipsets. It may be much more difficult to keep up with newer standards with the pace at which AMD is currently used to releasing CPU cores. It's not as easy as you might think. wbmw