Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (69354)	1/29/2002 1:04:34 PM
From: pgerassi	Respond to of 275872

Dear Joe: In the post to Tench, I stated that the switch is inside each Hammer CPU. Clawhammer needs at least a 4 way (1 to the core, 1 to a memory channel and 2 for the external HT links for a total of 4). The dual channel Clawhammer needs a 5 way and the 3 HT link dual core dual channel Sledgehammer needs a 7 way (although 3 3 way switches (1 for the two cores to the internal hub, 1 for the dual memory cores to the hub and 1 for the internal hub itself) plus a 4 way for the 3 HT Links to the internal hub but, at a cost of 3 times the latency of a switch. According to the diagram put out by AMD the main hub switch has a port to a switch connecting two cores, a port to a memory controller handling two channels and 3 ports for the 3 external links for a total of 5 ways. Only the main switch would need to change to go higher than 8 way SMP, it needs to be 6 way for 16 way SMP, 7 way for 32 way SMP and so on. The extra ways only to reduce the maximum number of hops to get from any core to any other's resources be it core, memory or I/O. Pete