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To: Tenchusatsu who wrote (69550)1/30/2002 5:00:22 PM
From: dale_laroyRead Replies (1) | Respond to of 275872
 
>The interleaving could be either fine-grained (e.g. 64B cachelines) or course-grained (e.g. 512MB blocks).<

So, would 4KB PMMU page interleaving be fine-grained or course grained?



To: Tenchusatsu who wrote (69550)1/30/2002 5:00:29 PM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Tench: Don't think of it like two overlapping address spaces, but more like one global address space split across two memory interfaces.

Ahh.. ok, thanks.

But how do you make sure that data that has to be accessed by processor#1 is located in processor#1's memory more than 50% of the time? Or is that just tough luck? (If it isn't directly feasible, maybe it would be possible to reserve some of the local memory as a sort of L3 cache?)

Thanks again,

fyo


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