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To: Tenchusatsu who wrote (69555)	1/30/2002 6:50:30 PM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

>I think what you are talking about is different and separate from what I'm talking about. How the OS interleaves pages doesn't matter, except perhaps from a performance perspective. If the interleaving on the Hammer memory system is fine-grained, that means a 4K page would span both memory interfaces.< Actually, I'm not exactly thinking about how the OS interleaves pages, but rather along the lines of coherency. Suppose that for coherency purposes the processors only communicated update information on a PMMU page basis rather than for individual cache lines. Example: The hierarchy is as follows: Timberwolf (my name for the server version of K9) has L1 cache and L2 cache, with the L2 TLB cache doubling as an L3 cache controller. External memory is multiported, with each stick having eight ports that are each eight bits wide, and each port accessing eight SRAM lines capable of caching one DRAM page each. In a single processor Greyhound (consumer version of K9) processor configuration, all eight ports would be configured in parallel to provide a single 64-bit wide transfer to the processor (actually eight parallel 8-bit transfers to separate 8-bit transfer registers). In an eight processor Timberwolf configuration, sixteen sticks would each supply one 8-bit channel to each of the eight Timberwolf processors, thus providing an independent 128-bit channel to each Timberwolf processor. The eight-way controller hub would keep track of coherency on a PMMU page by PMMU page basis with dedicated HT links to the Timberwolf processors being used to transmit PMMU page activity to the memory controller hub.