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To: kapkan4u who wrote (71062)2/8/2002 1:48:24 AM
From: THE WATSONYOUTHRespond to of 275872
 
I think you are confusing floating body and history effect. Floating body actually helps PD SOI performance due to G-B coupling, while the switching history effect requires a "history guardband" frequency during test. In addition, floating body hurts performance in bulk stack circuits, while it has no effect in PD SOI stack circuits.

Yes... and the history effect (from what I've seen) is not as large as Intel claims. I don't know how Intel gets around the body effect on bulk stacked circuits. Perhaps, this is where the dynamic well biasing comes in?? Sounds very complicated. I remember when all you had to worry about was one NFET and one PFET. Now you have two different gate oxide thicknesses to support both high voltage devices for I/O as well as low voltage devices for performance. Then you have both high and low Vt NFETs and PFETs. Now it sounds like you will have well biased devices as well. The complexity of these processes just keeps getting greater and greater.

THE WATSONYOUTH



To: kapkan4u who wrote (71062)2/8/2002 11:10:10 AM
From: wanna_bmwRespond to of 275872
 
Kap, I'm just going to have to trust you on that. Thanks for the explanation.

wbmw