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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (71212)	2/8/2002 7:58:48 PM
From: Elmer	Read Replies (2) \| Respond to of 275872

In the case of my hypothetical Banias, the CPU<->chipset connection would handle only the non-memory communication. This would logically require less pins, but it should be possible to make it a subset of the "full FSB". You're sort of describing what Timna was. The connection to the i/o subsystem is what Intel calls "hublink". A small pincount highspeed interface to the controller for PCI, USB, EIDE etc. The server-banias would then feature a different pin-out and have the integrated memory controller disabled. Am I making any sense? Sure it's possible to do but what would be the advantage? Are you looking for a way to provide SMP from this hypothetical Banias core with ondie MC and no external FSB? A sort of one size fits all die? BTW I hope it's clear that this discussion is purely hypothetical and not to suggest that Banias does or doesn't follow this architecture. EP