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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (158351)	2/11/2002 6:26:19 PM
From: Tenchusatsu	Respond to of 186894

Ali, I must be misunderstanding you. If you can find all the bugs pre-silicon, then obviously you don't need to validate post-silicon, and you can ship right after first tapeout. That's a manager's dream, but it just doesn't happen no matter how much time you spend validating pre-silicon. Yeah, it's tortuous to debug on actual silicon, but there's nothing that can be done about it. Bugs will escape to silicon, both the functional kind and the circuit kind. It's possible to workaround both kinds of bugs (but not all) with FIBs. That's preferable to waiting for a new silicon spin because often the bug is blocking other functionality that needs to be tested post-silicon. Of course the fix is also validated in pre-silicon simulation, but that just can't cover all the test vectors that a post-silicon environment can. Of course, pre-silicon validation tries to minimize the bugs that make it to post-silicon. But as long as there are bugs escaping to silicon, there will be a necessity for post-silicon validation, and a necessity for FIBs. Tenchusatsu