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vanshardware.com
NEWS
August 3rd, 2001
AMD's K8 Appears
A source who wishes to remain anonymous has told VHJ that Dresden has been producing K8 SOI samples for analysis. Apparently the first such chip appeared sometime last month. We hope to announce more in the coming weeks. "K8" is an alternative designation for AMD's upcoming "Hammer" family of 64-bit processors. Sampling this early suggests that AMD is well ahead of its published roadmaps.
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To: jcholewa who wrote (16496)
From: Y. Samuel Arai Monday, Oct 30, 2000 1:52 AM ET
Reply # of 16665
JC: I emailed you, but I'll post my translation here too.
This link:
watch.impress.co.jp
Translated reads:
AMD Hammer: Layout completed, Tapeout by year-end
What sort of CPU is the next generation Hammer family? AMD’s Bob Mitton (Enterprise Products Product Marketing, Computation Products Group) spoke to us in two different occations, at the IDF and MPF.
Q: Where are you now in the development of the Hammer?
A: We just completed the chip layout. We’re scheduled to complete tape out by year-end. Hardware sampling will begin next year. At that time, I can speak more freely about the hardware.
Q: Will Hammer utilize 0.18um or 0.13um process?
A: Hammer will begin with 0.18um, then switch to 0.13um process.
Q: Will performance differ between the 32 bit mode and 64 bit modes?
A: x86-64 processor itself is a full 64-bit architecture. There will be no parts that are 32-bit only. The processor data paths are 64 bits, and in the 32 bit mode, Hammer is designed to utilize the lower 32 bit paths only. The hardware operates identically in both modes. Thus, the performance will be the same in either mode.
Our processor was not designed by integrating two 32-bit processors together to produce a 64 bit processor. Also, in the 32 bit mode, we do not pack two 32 bits of data into the 64 bit space. Packing the bits may first seem likely to improve performance, but there are trade-offs. Specialized logic would be required and it would overly complicate the processor design.
We decided to simply incorporate a 32-bit mode within a 64-bit architecture. We believe the simpler the design, the more performance we can get out of the CPU. Therefore, the performance in both the 32-bit and 64-bit modes are the same, and it should be quite powerful as a 32-bit CPU.
Q: Will the Hammer have a performance edge over the Athlon (running 32-bit code)?
A: The Hammer will be equal to or faster than the Athlon.
Q: If your next CPU was designed as a 32-bit only CPU, wouldn’t you have been able to further improve the performance of the processor?
A: We could have designed a 32-bit only CPU to be smaller than the Hammer. But this has nothing to do with performance. Also, with our design, a 32-bit only die-size would have been less than 10% smaller than our 64-bit design. The difference would have been minimal. If we were to design another 32-bit CPU as well as a 64-bit CPU, we would have needed two design teams, and two different architechtures would lead to some confusion amongst the customers. Thus, we decided to introduce the 64-bit architecture that will work for everyone.
Q: Is the hammer CPU core basically an Athlon core expanded to 64 bits, or are there additions like a much deeper pipeline cache?
A: AMD considers the Hammer to our 8th generation CPU. There are very big differences between the Athlon and Hammer implementations. When announced, you’ll see that the Hammer incorporates a lot of brand new engineering and technology. But this doesn’t mean that the Hammer doesn’t incorporate anything we’ve learned from the Athlon. And like the Athlon, it will have full 32-bit code compatibility, be low-cost, and easy for OEM manufacturers to implement.
Q: Is the Hammer a completely different design than the Athlon?
A: The design is fairly different. Many things like the execution and I/O units will have a brand new design incorporated in them. However, the basic operation will be the same. It will not be a radically new design.
Like the Athlon, Hammer will have variations
Q: Does AMD consider the 64 bit architecture to be useable not only on Servers and Workstations, but on desktop PCs as well?
A:Intel IA-64 architecture is limited to the high-end server line of products. However, x86-64 architecture has no such limitations. Because the implementation costs will be very low, the x86-64 chips will be easily useable on the desktop.
Q: Does this mean that the Hammer family will have mobile and desktop versions like the Athlon?
A: Probably. X86-64 adoption will be determined by market demand. Even on desktops, video and graphics have increased CPU requirements, and they keep rising. Also, we wouldn’t be surprised if it is adopted for use in handheld and palmtop devices. For example, to access a network with a mobile phone, 64-bit encoding/decoding would be very useful.
Q: Is the first hammer slated for the server or the desktop?
A: The first hammers will be designed for the workstation and performance desktop markets. Then the server, then desktop, then mobile implementations will be released. This is basically the same order of adoption for the Athlon. It could take some time.
Q: AMD has a lot of support from the Linux world, but for PCs, support from Microsoft is probably needed.
A: There will be a lot of support needed from Microsoft. We have plans to have further discussions with Microsoft. We’ve already given them the specifications.
SSE support through 64-bit mode
Q: X86-64 architecture has SSE registers. Does this mean Hammer will support the SSE instruction set?
A: Hammer will support SSE-2. However, it won’t be supported in the same way that Intel implements it. IEEE floating point is the only thing supported in the [Long mode (x86-64 new mode)]. One reason we must support SSE, is because x87 floating point is different from IEEE floating point. To utilize both, we need a different instruction set. We thought about creating a new instruction set, but this also has problems. Our philosophy was to utilize an API and architecture with which the programmers are already familiar. SSE2 has a floating point API, which meets our requirements. Thus, instead of developing our own API, we decided to use SSE2, as this is much easier for everyone to understand. This has nothing to do with the Intel/AMD competition. Its standard and its widely used; these are the reasons we chose to use SSE.
Q: Is this the same thing as the announcement last year regarding “Technical Floating Point” (TFP) that would be supported by x86-64?
A: Yes. TFP is SSE.
Q: Is floating point the only thing supported? Will it also do SIMD Integer calculations?
A: The other instructions will only be supported by Intel.
Q: Will 3Dnow! Continue to be supported?
A: It will be supported in 32-bit mode. Under 64-bit mode, 64-bit integer operations and SSE floating point operations will be used.
Q: Are the SSE2 and x87 execution units the same?
A: I can’t comment on that.
Instruction-level parallelism Opinions
Q: With IA-64, Intel not only went to 64-bit, but went with a completely new architecture. What are your thoughts on this?
A: I can’t agree with their approach. Intel says they get a performance advantage through ILP (Instruction Level Parallelism). This is only true when ILP can be implemented effectively. In my experience, ILP is only useful in very limited applications.
For example, it used to be thought that RISC architecture had an advantage over CISC architecture. But code size increases with RISC, so memory access was always a trade-off, thus, was not much faster than CISC architecture. Today, Athlon is faster than the fastest RISC CPUs. Looking at these facts, it becomes clear that ILP does not give you a performance advantage. If it weren’t true, the x86 architecture would have been outclassed by the RISC machines a long time ago. We believe that rather than changing the instruction set, it is more important to change the way the current instruction set is implemented.
Q: Intel says that the x86 instruction set is the limiting factor to higher performance.
A: That’s what they say. However, we are ahead of them in x86 technology and engineering. This is not because we changed the instruction set. This is because of the way in which we implemented the x86 instruction set. If Intel really believes that a new instruction set is necessary to improve performance, then they should cut their Pentium line of CPUs. But, they won’t do this. Thus, what they say cannot be believed.
Q: Then do you believe that the IA-64 architecture will not be successful?
A: IA-64 is a very large chip design. It can only be seen as a high-end server product. Production costs will be enormous. It is also difficult to adapt software to it. Thus the market for Merced will be very small, and it will take a very long time for Intel to realize any returns on their investment. Their architecture, and their business tactics, does not make good business sense.
Compared to Merced, AMD’s 64 bit architecture will be very easy to adapt. The market for this product will be huge. Our approach makes it very easy for OEM manufacturers, and IT managers to adapt.
Mustang will also use an exclusive cache
Q: Pentium 4 will be introduced at 1.4Ghz and above. Can Athlon compete with this?
A: I haven’t seen the Pentium 4 yet, but the architecture is not very impressive. In order to use higher clock-speeds, they’ve developed a 20-stage pipeline architecture. This gives them the clockspeed, but the tradeoffs are large. A cache-miss will lead to their having to fill the entire 20 stages again. Performance will be greatly limited by the penalties incurred by a cache miss. Average code contains one branch instruction for every 6 instructions. Thus the P4 will incur quite an overhead. The clockspeed may be high, but the benchmarks will show that the performance is not up to par.
Q: Pentium 4 is slated to reach 2Ghz fairly soon. Can Palomino (new Athlon) reach 2Ghz?
A: Of course. Why wouldn’t it?
Q: Athlon uses an exclusive cache architecture. Will Mustang slated for Servers/Workstation also use the same architecture?
A: All Athlons will utilize the Exclusive-cache architecture.
Q: About how many pins will the 760MP chipset for the dual-athlon contain?
A: About 900. |
