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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dale_laroy who wrote (71842)	2/18/2002 10:49:18 AM
From: hmaly	Read Replies (3) \| Respond to of 275872

Dale Re...In analysing the distribution of transistors on the P4 (Willamette), Paul DeMone came to the conclusion that P4 has a lot of "dark" transistors, that is transistors that have no claimed function. It is hypothesized that these are for implementing Jackson Technology, which may not be functional in Willamette nor even Northwood.<<< Then we all agree, you, I and Paul Demond, that the P4 at 130 mm isn't an efficient design. It may become one later, but it won't be for 2 - 3 yrs. However, at 130nm AMD can not muster sufficient volume to cripple Intel. All Intel has to do is sit back, let AMD fight the price war alone, and charge premium prices for that market share AMD can not service. Then, Intel can fight a down and dirty price war at the 90nm node where Jackson Technology may kick in and die size will not be as big an issue, since package price will make up a much higher percentage of total costs.<<<<<<< And that was my exact point. Intel is in no shape to fight a price war now. However, one of Intel's big problems with waiting is that at least 2 of those 300mm fabs come on line this yr. Which means Intel will be forced to address over capacity problems before 90 mm is available, or engage in a price war when overcapacity rears its ugly head.. All bets ar off if McKinley is a unqualified success this summer. One way to do this is with L2 cache, they doubled P4 L2 cache at 130nm, and could very easily double it again at 90nm. If AMD matches this with the 90nm Clawhammer, Clawhammer will not be nearly as small as AMD anticipates. If they don't, Intel could end up demanding even more of a price premium than they currently do.<<<<<<<< To me this part of your argument doesn't seem logical. Why would AMD do that when the current XP at .18 with it's current L2 cache outperforms NW at 130 nm with the bigger cache. AMD going to 130 nm, and later SOI will maintain or improve the edge XP already has; without going to a big L2. Clawhammer will be an even bigger improvement. Sometimes there is more than one way to skin a cat. AMD has shown the ability to improve performance without a huge L2, and consequently a big die. Which will in my estimation force Intel to give up its big die theory, in favor of AMD's more efficient design. But, even at 130nm the cost of P4 is well below $100 per unit of production. <<< And so will AMD's costs/chip drop below $60 at 130 nm. Percentage wise, AMD's should drop even further as AMD isn't likely to put on a bigger cache. Just a guess. From the CC, Jerry really believes he has Craig by the bas on this one, and I don't think AMD will give this edge up easily. And, even AMD claims that Intel will slash their silicon costs by as much as 30% with the move to 300mm wafers.<<<<<<<** I will grant you that if you grant me the fact that 300 mm chips have other expensive costs associated with it. Not to mention the fact that Intel will have to shutter a lot of those 200 mm fabs. Intel needs to go to 300 mm because of the big die problem. AMD doesn't, and can change over at its leisure, and on the cheap; as was demonstrated by the JV partnership.

To: dale_laroy who wrote (71842)	2/18/2002 11:40:07 AM
From: Tony Viola	Read Replies (1) \| Respond to of 275872

Re: >It is quite possible that a 90mm2 65nm P4 on 300mm wafers could be cost competitive with a 65mm2 65nm Clawhammer on 200mm wafers. Gotta say, Dale, that you really like to look way down the road on this stuff. So many things can change between now and then. It's like, if I'm driving from Boston to San Francisco, I have to be a lot more concerned about a snowstorm happening in New York right now than whether I'm going to enter SF via the Golden Gate or the Bay Bridge. But heck, it's your Internet connection and your message board. Tony

To: dale_laroy who wrote (71842)	2/18/2002 3:01:16 PM
From: ptanner	Respond to of 275872

Dale, re: " Intel's big die theory is that they can derive sufficient utility from a big die to force AMD to match, or at least nearly match, the die size of Intel's processor to deliver competitive performance." I am very skeptical of big die theory (BDT) as an Intel vs competition program. I see larger dies sizes as being more the result of market needs and marketing needs. Market needs I consider to be the continued development of new CPU features and applications which require additional processor die space. Marketing needs I see as the need to compete with all the existing processors presently providing acceptable service but for which a "need for speed or features" available in a new processor may succeed. From this, I think Intel (and AMD) then balance the benefits from larger dies with the costs for research, capital investment, and the estimated production cost of the final product. Then decisions are made based on the projected market: scrap this one or build some more fab capacity. A "build it and they will come" approach to capital investment is ludicrous. Having ample cutting edge capacity to ensure total market production capacity of the products you plan to bring to market, however, would be a reasonable investment to be prepared should the opportunity avail itself and to prevent market share loss. Intel's present approach to fab upgrade/expansion (build new ones) is more expensive up front than AMD's (replace equipment in Fab 30). However, the old fabs are not idle and represent valuable capacity and expertise for the production of other products. Sure, some of the oldest fabs may fall idle as they can no longer productively be used for current products (like AMD's closing of 2 old fabs near Austin) but the life cycle isn't limited to a couple years of CPU production. JMHO. -PT