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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: wanna_bmw who wrote (159517)	2/20/2002 8:50:24 PM
From: Dan3	Read Replies (4) \| Respond to of 186894

Re: Which is it, Ali? Are you wrong about the Physical limits of SRAM cells, or does AMD run their cache at 833MHz? Do you still plan on bullshitting yourself out of this one? Must you try to emulate Paul and be a rude jerk? I know it's his nature that's spreading through the thread, not yours, but still... P4 has a short latency 2 cycle L1 cache, while AMD has a 3 cycle L1. Since AMD's design allows more time to access the L1, it can operate at a higher frequency - think of it as a long pipeline "netburst" style L1 cache. :-) At only 8K, the NetBurst L1 data cache is only half the size of the Pentium III's, and just a fraction of the size of the Athlon's 64K data cache. Intel chose this small cache size because smaller caches have lower latencies. While the Athlon and PIII data caches have a three-cycle latency, the P4's L1 data cache latency is two cycles. It's all part of the plan to keep that deep pipeline well fed. tech-report.com

To: wanna_bmw who wrote (159517)	2/20/2002 10:32:28 PM
From: Ali Chen	Read Replies (1) \| Respond to of 186894

"You distinctly made the claim that SRAM cells are hitting a physical limit in the Pentium 4....If Intel can't run their cache past 1.1GHz because of physical limits at .13u manufacturing, then..." Then do not pretend to be an idiot. You perfectly know that the basis of my opinion was Intel's technology paper about 0.18um manufacturing, where P4 hit 2000 "MHz", or "MarketingHz", but the SRAM was topped at around 1000MHz. And I widely publicized that findings. You certainly understand that on 0.13 the limit will be somewhat higher, but the proportion must still hold. It is clear for anyone who have even a bit of understanding of digital logic design that Intel runs L2 cache as two interleaved blocks multiplexed at the input to execution units. - Ali