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To: Dan3 who wrote (72284)	2/22/2002 3:06:01 PM
From: combjelly	Respond to of 275872

"There's no prefetch on the Dell. The Dell uses a PIII. PIII doesn't have prefetch" But, Tualatins do. So maybe we should call them PIII.5? anandtech.com

To: Dan3 who wrote (72284)	2/22/2002 3:30:52 PM
From: semiconeng	Respond to of 275872

There's no prefetch on the Dell. The Dell uses a PIII. PIII doesn't have prefetch. Were you thinking SSE? Both have SSE, only the Athlon4 has prefetch. Actually, the chip noted is the P3M, and According to this, P3-M is the designation of the 0.13u P3: vr-zone.com "Intel officially rolled out its awaited 0.13-micron Pentium III processor-M series with speeds up to 1.13-GHz and three new 830 chip sets designed to take advantage of the new mobile Pentium III processor-M performance and low power characteristics" And according to this, there is data pre-fetch: hardocp.com Available at 1.13GHz and 1.20GHz System bus frequency at 133 MHz 256KB Advanced Transfer Cache (on-die,full speed Level 2 (L2) cache with Error Correcting Code (ECC)) Dual Independent Bus (DIB) architecture: Separate dedicated external System Bus and dedicated internal High-speed cache bus Internet Streaming SIMD Extensions for enhanced video, sound, and 3D performance Binary compatible with applications running on previous members of the Intel microprocessor line Dynamic execution micro architecture Power Management capabilities —System Management mode —Multiple low-power states Optimized for 32-bit applications running on advanced 32-bit operating systems Flip Chip Pin Grid Array (FC-PGA2) packaging technology; FC-PGA2 processors deliver high performance with improved handling protection and socketability Integrated high performance 16 KB instruction and 16 KB data, nonblocking, level one cache 256KB Integrated Full Speed level two cache allows for low latency on read/store operations Quad Quadword Wide (256 bit) cache data bus provides extremely high throughput on read/store operations. 8-way cache associativity provides improved cache hit rate on reads/store operations. Error-correcting code for System Bus data Data Prefetch Logic Semi