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To: Paul Engel who wrote (159874)	2/23/2002 6:41:20 AM
From: John F. Dowd	Respond to of 186894

Paul: The ability to subdivide, or partition, servers into a number of independent computers housed in the same hardware has several advantages. For one, partitioning means smaller machines are physically in the same place, not scattered around. This makes them easier to manage. Buying one big server and splitting it up can also be cheaper than buying many smaller machines. And partitioning allows for more efficient use of processing resources because a single, divided server can balance workloads across its partitions. For example, if there's a surge in Web site traffic, the divided server can automatically decrease the number of partitions devoted to inventory management and increase the number devoted to traffic. When the traffic dies down, it can restore the original allocations Sounds great but what happened to the reality of 9/11. Better to have a networked group of servers located in different locations for storage,back-up and security. SANS as I understand it can now be set up 1000's of miles apart with no loss of performance (CMNT). JFD

To: Paul Engel who wrote (159874)	2/24/2002 9:04:14 AM
From: Exciton	Read Replies (1) \| Respond to of 186894

Paul, Questions related to AMD's foundry agreements with UMC. When a foundry has multiple clients that it is trying to satisfy on a given process, are there significant trade-offs in process parameters that must be made to allow for production of the different chips on a single line? If UMC, for example, were trying to balance process parameters between NVIDIA graphics chips and AMDs processors, what types of trade-offs would be made and what impact would those trade-offs have on each party? I suppose the foundry could dedicate a given line in a fab to a particular high volume customer, but wouldn't that be rather inefficient unless the customer could guarantee maximum line utilization? A related question: If the process parameters at AMD's Dresden fab and UMC are significantly different for a given node, what complications might arise that would affect yield and performance? Would the chip designers have to modify the original design parameters for production on the UMC process?