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To: semiconeng who wrote (73240)	3/4/2002 5:17:47 PM
From: wanna_bmw	Respond to of 275872

Semi, Re: "Non-Blocking, full speed, on-die level 2 cache 8-way set associativity 256-bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle" Nice find. It looks like the cache is dual ported, too. wbmw

To: semiconeng who wrote (73240)	3/4/2002 5:22:06 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

semi, The "transfers data on each core clock" is very un-ambiguous, but "full speed, on-die level 2 cache" was a subject of a discussion, as far as which speed, since P4 has at least 4 clock domains. Based on your and wmbw's posts, I am changing my opinion on P4 L2 from most likely running at half (marketing) speed to most likely running at full speed. Joe