SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (73247)3/4/2002 6:04:23 PM
From: wanna_bmwRead Replies (2) | Respond to of 275872
 
Ali, Re: "According to Intel technological papers on 0.18um
process, their 6-T SRAM cell cannot run above 900MHz.
It was two years ago. I guess some improvements may
make it to 1.1 GHz and slightly above. There is absolutely
no way that their current SRAM cell can run at 2.2GHz,
it is physically impossible for this process, and
equally unlikely for the new 0.13um."

Sorry, but you're incorrect. I heard it from the horse's mouth. L2 Cache runs at full processor speed.

Of course it may totally blow your mind, but I thought I'd also mention that L1 data cache happens to run at 2x the processor speed (or 4.4GHz).

wbmw



To: Ali Chen who wrote (73247)3/4/2002 8:08:36 PM
From: PetzRead Replies (1) | Respond to of 275872
 
Ali, should have read your post first. I would consider the P4's L2 "ATC" cache as really resembling a 512 bit-wide interface at half speed rather than a 256 bit wide memory at full speed. Interleaving only works when the access pattern to the memory is 1-2-1-2-1-2-1-2-1-2, etc.

Petz


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News