To: hlpinout who wrote (95665 ) 3/4/2002 6:51:22 PM From: hlpinout Respond to of 97611 Charts at the link. -- Alpha-Itanium CPUs collide S'wonderful, S'marvellous... By Mike Magee, 04/03/2002 09:28:06 BST THE LATEST COMPAQ roadmap we've seen for the Alpha contrasts its performance with Intel's Itanium, and the latter is still lagging in performance terms. Compaq - when it was still talking to us - told us of the upgrade to the Alpha technology but its EV7 technology, expected to be released in April, looks like it will still whop just about every other competitor in the face with its performance characteristics. The EV7 will clock at speeds of around 1.2GHz, use 155W, and have a die size of 400 square millimeters on a .18 micron process, and with 1443 pins, compared to the 675 pins of EV68C. And around this time next year, the EV79 will clock at around 1.7GHz, will be made using 130 nanometer technology and silicon on insulator, with a die size of 300 square millimeters and using power of 120W. It tapes out in the the first quarter of next year for release in the first half of 2004, perilously close to the date the Itanic and the Alpha technology are supposed to become one. That's an awful long time for a shrink, isn't it? What's the story there? EV7 (Alpha 21364) has integrated level two cache, an integrated memory controller and an integrated network interface, with support for a lock step operation for high availability systems. Marvellous. The chip will be a seven layer baby, with 152 million transistors, 15 million of which are logic chip and 137 million of which will be SRAM. It can address an interesting 4TB of memory, with virtual page sizes of 64K, 2MB, 64MB and 512MB. The L2 cache on the die is seven way set associative with ECC, has 20GB/s read/write bandwidth, and 16 victim buffers for L1 to L2, and 16 victim buffers for L2 to memory. As we've pointed out before, the two memory controllers are Rambus based and directly connect to the processor. The integrated network interface has direct processor-to-processor interconnect, with four links, each being 6.4GN/s. with 18 nanoseconds processor to processor latency, creating an out of order network with adaptive routing, and having asynchronous clocking between processors, and with a 3GB/s IP interface per processor. Here's a diagram of the memory bandwidth, comparing it to other processors. And here's another which shows estimated SPEC200 1-CPU peak for the 1.2GHz Marvel agin the opposition. Of course the Itanium and the Alpha are not now in opposition, but you know what we mean. Moles at the Intel Developer Conference in SF last week whispered to us that if La thinks she can use all the hyperthreading the Alpha boys have as soon as it expects for its IA-32 families like Prescott, she can probably think again. µtheinquirer.net