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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: hmaly who wrote (73512)	3/5/2002 6:26:57 PM
From: semiconeng	Respond to of 275872

I am hardly a process engineer; but I thought I read somewhere that the thinner the lines, the deeper the lines would have to be to carry the current, and it would take more layers. Hummmm..... That would be more a Device Engineer question rather than a Process Engineer question. I can go over and ask if you want..... :-) Semi

To: hmaly who wrote (73512)	3/5/2002 9:02:50 PM
From: burn2learn	Read Replies (3) \| Respond to of 275872

How about the affect on yield due to more layers and product handling. More die lost to defects! or Time to market What is the average time it takes to get through a layer...add 3 more. or more metal = more resistance = more power = more heat...do you need SOI to deal with the added layers? or fab capacity, did you just shrink you capacity by adding more layers. same tools for the backend, just used again and again and again. Pretty neat issues to deal with in keeping the die small