SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Petz who wrote (73610)3/5/2002 11:37:00 PM
From: semiconengRead Replies (2) | Respond to of 275872
 
Adding more layers would decrease, not increase, the resistance, heat and power, because the vertical distance a signal would travel to find a shorter path on an additional layer is insignificant compared to the long, ciruitous path on fewer, but BIGGER layers. No way could you fit 100M transistors on a die without this many layers.

--There's no evidence that the path on the additional layer would be any shorter, or less ciruitous. It's been my experience that developers add extra metal layers, and extra process steps because they need to, not because they want to.

--Also, you are failing to take into account that the materials used for the via interconnects are not necessarily the same material used for the metal lines, and therefore there can very well be a speed penalty to adding additional Metal Layers.

But the first layer which builds the transistors takes MUCH longer than any of the others, so 50% more layers may only take 15% more time.
Petz


--I don't mean for this to sound rude, but you keep saying "The First Layer which builds the transistors". This is completely wrong. Transistors are not built on a First Layer at all. It takes multiple layers. So if you're not really too versed on building semiconductor transistors, can you please stop pretending that you do?

Thanks,
Semi