Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Petz who wrote (73637)	3/6/2002 10:28:09 AM
From: Pravin Kamdar	Respond to of 275872

Petz, I understand that the gates of the transistors are on one level while the sources and drains are on another, but I'm not sure you can properly call the 3-D structure to be "layers" of silicon, since most of each "layer" is the insulator. You could probably spend a little time with a book in this area, but the rest of your post makes sense. Pravin

To: Petz who wrote (73637)	3/6/2002 10:39:06 AM
From: Joe NYC	Respond to of 275872

Petz, And your assertion that having more layers available to route the signals will not reduce the average path length is absurd. I was going to comment about it as well, since it seemed counterintuitive to me, but I know next to nothing about how ICs are put together. But then, one of my job titles used to be a consultant, which gives you a license to to talk like an expert, even give advice about subject you know absolutely nothing about. <g> Joe

To: Petz who wrote (73637)	3/6/2002 1:19:00 PM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

>Therefore, going from six to nine metallization layers does not increase the number of process steps, or the time to build the chip, by anything close to 50%.< I believe that the number of mask steps (individual masks not steps to process the all the masks) for the device layer ranges from four to six, depending upon the types and uniformity of the devices. Of course, I read this nearly a decade ago, and things can change a lot in a decade, even assuming what I read was correct. My guess is that AMD increased their number of mask steps by about 25% in going to 9 layers of metal interconnects. For the record, the decision to go to a higher number of metal interconnects is often related to shrinking the die area. A reasonable assumption would be that Clawhammer would be at least 50% larger with 6 layers of metal interconnects than with 9 layers of metal interconnects.